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31. 发明申请

US20120201068A1 STACKED SEMICONDUCTOR DEVICE 有权
标题翻译：堆叠半导体器件
公开(公告)号：US20120201068A1
公开(公告)日：2012-08-09
申请号：US13502093
申请日：2010-09-24
申请人： Frederick A. Ware
发明人： Frederick A. Ware
IPC分类号： G11C5/06 , H01L21/50 , H01L23/522
CPC分类号： G11C11/4093 , G11C5/04 , G11C11/4096 , G11C17/16 , G11C17/18 , H01L24/05 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L2224/05552 , H01L2224/05568 , H01L2224/08148 , H01L2224/8013 , H01L2224/80132 , H01L2224/80897 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.
摘要翻译：公开了一种包括多个半导体管芯的叠层半导体器件。每个模具具有相对设置的第一和第二表面，在每个表面上形成有垫。多个通孔将第一表面上的相应焊盘连接到第二表面上的相应焊盘。通孔包括耦合到半导体管芯上的相应I / O电路的第一组通孔，以及未耦合到半导体管芯上的I / O电路的第二组通孔。多个半导体管芯被堆叠，使得多个半导体管芯中的第一个半导体管芯中的第一组通孔与第二组通孔中的至少一部分中的相应的通孔对准多个半导体管芯。

32. 发明授权

US08218382B2 Memory component having a write-timing calibration mode 有权
标题翻译：具有写定时校准模式的存储器组件
公开(公告)号：US08218382B2
公开(公告)日：2012-07-10
申请号：US13228070
申请日：2011-09-08
申请人： Frederick A. Ware
发明人： Frederick A. Ware
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G06F1/10 , G06F13/1689 , G06F13/4243 , G11C7/1072 , G11C7/22 , G11C8/18 , G11C11/409 , G11C2207/2254
摘要： In memory component having a write-timing calibration mode, control information that specifies a write operation is received via a first external signal path and write data corresponding to the write operation is received via a second external signal path. The memory component receives multiple delayed versions of a timing signal used to indicate that the write data is valid write data, and outputs signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay interval between outputting the control information on the first external signal path and outputting the write data on the second external signal path.
摘要翻译：在具有写入定时校准模式的存储器组件中，经由第一外部信号路径接收指定写入操作的控制信息，并且经由第二外部信号路径接收与写入操作相对应的写入数据。存储器组件接收用于指示写入数据是有效写入数据的定时信号的多个延迟版本，并且输出与定时信号的多个延迟版本对应的信号，以使得能够在存储器控制器中确定输出关于第一外部信号路径的控制信息，并在第二外部信号路径上输出写入数据。

33. 发明申请

US20120173811A1 Method and Apparatus for Delaying Write Operations 审中-公开
标题翻译：延迟写入操作的方法和装置
公开(公告)号：US20120173811A1
公开(公告)日：2012-07-05
申请号：US13421753
申请日：2012-03-15
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the DRAM. The first code is to be sampled by the DRAM and held by the DRAM for a first period of time before it is issued inside the DRAM. The interface is further to transmit the first data that is to be sampled by the DRAM after a second period of time has elapsed from when the first code is sampled by the DRAM. The interface is further to transmit a second code, different from the first code, to indicate that second data is to be read from the DRAM. The second code is to be sampled by the DRAM on one or more edges of the external clock signal.
摘要翻译：一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括用于向DRAM发送第一代码以指示要将第一数据写入DRAM的接口。第一代码将由DRAM采样并由DRAM在DRAM发出之前的第一时间段内保持。该接口在从DRAM的第一代码被采样起经过了第二时间段之后，进一步发送由DRAM采样的第一数据。该接口还用于发送与第一代码不同的第二代码，以指示要从DRAM读取第二数据。第二个代码由外部时钟信号的一个或多个边缘上的DRAM采样。

34. 发明授权

US08214616B2 Memory controller device having timing offset capability 有权
标题翻译：具有定时偏移能力的存储器控制器装置
公开(公告)号：US08214616B2
公开(公告)日：2012-07-03
申请号：US11754995
申请日：2007-05-29
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F13/36
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset such that the first data arrives at a first memory device in accordance with a predetermined timing relationship with respect to a first transition of the clock signal, and a third transmitter to output second data suing a second timing offset such that the second data arrives at a second memory device in accordance with a predetermined timing relationship with respect to a second transition of the clock signal.
摘要翻译：公开了一种存储器控制器。在一个特定的示例性实施例中，存储器控制器可以包括：第一发射器，用于相对于时钟信号同步地输出第一和第二写入命令;第二发射器，使用第一定时偏移来输出第一数据，使得第一数据到达第一根据与时钟信号的第一次转换相关的预定定时关系，存储器件;以及第三发送器，输出第二数据，该第二数据产生第二定时偏置，使得第二数据按照预定定时到达第二存储器件关于时钟信号的第二转换。

35. 发明授权

US08195907B2 Timing adjustment in a reconfigurable system 有权
标题翻译：可重构系统中的时序调整
公开(公告)号：US08195907B2
公开(公告)日：2012-06-05
申请号：US12258680
申请日：2008-10-27
申请人： Frederick A. Ware , Ian Shaeffer , Scott C. Best , Craig E. Hampel
发明人： Frederick A. Ware , Ian Shaeffer , Scott C. Best , Craig E. Hampel
IPC分类号： G06F1/08 , G06F13/16
CPC分类号： G06F13/4243
摘要： This disclosure provides a method for adjusting system timing in a reconfigurable memory system. In a Dynamic Point-to-Point (“DPP”) system, for example, manufacturer-supplied system timing parameters such as access latency and maximum clock speed typically reflect a worst-case configuration scenario. By in-situ detecting actual configuration (e.g., whether expansion boards have been inserted), and correspondingly configuring the system to operate in a mode geared to the specific configuration, worst-case or near worst-case scenarios may be ruled out and system timing parameters may be redefined for faster-than-conventionally-rated performance; this is especially the case in a DPP system where signal pathways typically become more direct as additional modules are added. Contrary to convention wisdom therefore, which might dictate that component expansion should slow down timing, clock speed can actually be increased in such a system, if supported by the configuration, for better performance.
摘要翻译：本公开提供了一种用于在可重构存储器系统中调整系统定时的方法。在动态点对点（“DPP”）系统中，例如，制造商提供的系统定时参数，例如访问延迟和最大时钟速度通常反映最坏情况的配置方案。通过原位检测实际配置（例如，是否插入了扩展板），并且相应地将系统配置为以特定配置的方式运行，可能排除最坏情况或接近最坏情况的情况，系统时序可以重新定义参数以达到比常规级别更高的性能; DPP系统尤其如此，其中信号路径通常随着附加模块的添加而变得更直接。因此，与惯例智慧相反，这可能决定组件扩展应该减慢时序，如果配置支持，这样的系统实际上可以增加时钟速度，以获得更好的性能。

36. 发明授权

US08132077B2 Unidirectional error code transfer for both read and write data transmitted via bidirectional data link 有权
标题翻译：通过双向数据链接传输的读取和写入数据的单向错误代码传输
公开(公告)号：US08132077B2
公开(公告)日：2012-03-06
申请号：US13013779
申请日：2011-01-25
申请人： Yuanlong Yang , Frederick A. Ware
发明人： Yuanlong Yang , Frederick A. Ware
IPC分类号： G11C29/00
CPC分类号： G06F11/0727 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/073 , G06F11/0751 , G06F11/076 , G06F11/0793 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1044 , G06F11/1068 , G06F11/1402 , G06F13/4286 , H03M13/09 , H03M13/29 , H03M13/2906 , H03M13/611 , H04L1/0003 , H04L1/0008 , H04L1/0061 , H04L1/08 , H04L1/1867 , H04L2001/0093
摘要： A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
摘要翻译：控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。耦合到链路接口的发射机是发送写入数据。延迟元件耦合到编码器的输出。耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

37. 发明授权

US08112608B2 Variable-width memory 有权
标题翻译：可变宽度内存
公开(公告)号：US08112608B2
公开(公告)日：2012-02-07
申请号：US12631614
申请日：2009-12-04
申请人： Richard E Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F12/08
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.
摘要翻译：描述了存储器系统，其中存储器核心组织随设备宽度而变化。所访问的物理存储器组的数量随着器件宽度而减少，导致相对较窄的存储器配置的功率消耗减少。增加用于窄内存宽度的逻辑内存库的数量可以减少存储体冲突的可能性，从而提高速度性能。

38. 发明申请

US20110248407A1 Process For Making a Semiconductor System 有权
标题翻译：制造半导体系统的过程
公开(公告)号：US20110248407A1
公开(公告)日：2011-10-13
申请号：US13166996
申请日：2011-06-23
申请人： Frederick A. Ware , Ely K. Tsern , Ian P. Shaeffer
发明人： Frederick A. Ware , Ely K. Tsern , Ian P. Shaeffer
IPC分类号： H01L21/768 , H01L23/538
CPC分类号： H01L21/768 , H01L25/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/05599 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/10253 , H01L2924/00
摘要： Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.
摘要翻译：包括第一设备和第二设备的多个设备具有操作电路和相对的第一和第二表面。第一和第二电触点形成在第一表面处，而在与第一电触点相对的第二表面处形成第三电接触。第一电触头电连接到操作电路，并且第二电触头电连接到第三电触头。随后堆叠第一装置和第二装置，使得第二装置的第一表面位于第一装置的第二表面附近，使得第二装置的第一电触点与第一装置的第三电触点对准。第二器件的第一电接触电连接到第一器件的第三电接触件。

39. 发明申请

US20110238870A1 Memory System With Command Filtering 审中-公开
标题翻译：带有命令过滤的内存系统
公开(公告)号：US20110238870A1
公开(公告)日：2011-09-29
申请号：US13131557
申请日：2009-11-17
申请人： Frederick A. Ware , Wayne Richardson , Kishore Kasamsetty
发明人： Frederick A. Ware , Wayne Richardson , Kishore Kasamsetty
IPC分类号： G06F13/28
CPC分类号： G11C29/56 , G01R31/3171 , G11C29/028 , G11C29/48 , G11C29/50012 , G11C29/56012
摘要： A memory system includes a memory controller coupled to at least one memory device via high-speed data and request links. The timing and voltage margins of the links are periodically calibrated to reduce bit error. The high-speed request links complicate calibration because commands issued over the uncalibrated request links can be erroneously interpreted by the memory device. Misinterpreted commands can disrupt the calibration procedure (e.g., a write command might be misinterpreted as a power-down command). The memory controller addresses this problem using a separate, low-speed control interface to issue a filter command that instructs the memory device to decline potentially disruptive requests when in a calibration mode.
摘要翻译：存储器系统包括经由高速数据和请求链路耦合到至少一个存储器设备的存储器控制器。链路的定时和电压裕度被定期校准，以减少位误差。高速请求链接使校准变得复杂，因为通过未校准的请求链接发出的命令可能被存储器件错误地解释。错误解释的命令可能会中断校准过程（例如，写命令可能被误解为掉电命令）。存储器控制器使用单独的低速控制接口来解决这个问题，发出一个过滤器命令，指示当处于校准模式时存储器件可能会破坏潜在的破坏性请求。

40. 发明申请

US20110235459A1 CLOCK-FORWARDING LOW-POWER SIGNALING SYSTEM 有权
标题翻译：时钟转换低功率信号系统
公开(公告)号：US20110235459A1
公开(公告)日：2011-09-29
申请号：US13132091
申请日：2009-07-09
申请人： Frederick A. Ware , Robert E. Palmer , John W. Poulton
发明人： Frederick A. Ware , Robert E. Palmer , John W. Poulton
IPC分类号： G11C8/18 , H04L7/02
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路装置包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

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