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31. 发明授权

US07511528B2 Device and method to eliminate step response power supply perturbation 失效
标题翻译：消除阶跃响应电源扰动的装置和方法
公开(公告)号：US07511528B2
公开(公告)日：2009-03-31
申请号：US11461788
申请日：2006-08-02
申请人： Igor Arsovski , Joseph A. Iadanza
发明人： Igor Arsovski , Joseph A. Iadanza
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00346
摘要： A system and method for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.
摘要翻译：公开了一种用于在集成电路上的电压岛上电/掉电期间消除阶跃响应电源扰动的系统和方法。 IC芯片与主电源通信并且包括至少一个电压岛。芯片的电压岛上的主要头部通过主头电源路径与主电源通信。芯片的电压岛上的次级标题通过辅助电源通路与二次电源通信。与IC芯片和电压岛通信的控制解码器调节主集线器和副集线器的状态。

32. 发明申请

US20080030223A1 DEVICE AND METHOD TO ELIMINATE STEP RESPONSE POWER SUPPLY PERTURBATION 失效
标题翻译：消除步骤响应电源扰动的装置和方法
公开(公告)号：US20080030223A1
公开(公告)日：2008-02-07
申请号：US11461788
申请日：2006-08-02
申请人： Igor Arsovski , Joseph A. Iadanza
发明人： Igor Arsovski , Joseph A. Iadanza
IPC分类号： H03K19/173
CPC分类号： H03K19/00346
摘要： A system and method for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.
摘要翻译：公开了一种用于在集成电路上的电压岛上电/掉电期间消除阶跃响应电源扰动的系统和方法。 IC芯片与主电源通信并且包括至少一个电压岛。芯片的电压岛上的主要头部通过主头电源路径与主电源通信。芯片的电压岛上的次级标题通过辅助电源通路与二次电源通信。与IC芯片和电压岛通信的控制解码器调节主集线器和副集线器的状态。

33. 发明授权

US11010133B2 Parallel-prefix adder and method 有权
公开(公告)号：US11010133B2
公开(公告)日：2021-05-18
申请号：US16921603
申请日：2020-07-06
申请人： Ranjan B. Lokappa , Igor Arsovski
发明人： Ranjan B. Lokappa , Igor Arsovski
IPC分类号： G06F7/506
摘要： An adder includes a primary carry bit generation circuit and a summing circuit. The primary carry bit generation circuit is configured to generate first carry bits for a first number of pairs of bits from first and second operands, and to generate second carry bits for a second number of pairs of bits from the first and second operands. The second number of pairs being different than the first number of pairs. The summing circuit is configured to generate first sums by adding bits of pairs from the first and second number of pairs and the first and second carry bits. The summing circuit is configured to generate second sums by adding bits of other pairs of the bits from first and second operands than the pairs in the first and second number of pairs and additional carry bits generated when adding the bits of the other pairs.

34. 发明申请

US20120075919A1 Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability 有权
标题翻译：用于调整字面上升电压的方法和系统，以提高相对于SRAM单元稳定性的产量
公开(公告)号：US20120075919A1
公开(公告)日：2012-03-29
申请号：US12892191
申请日：2010-09-28
申请人： Igor Arsovski , George M. Braceras , Kevin W. Gorman , Robert M. Houle , Harold Pilo
发明人： Igor Arsovski , George M. Braceras , Kevin W. Gorman , Robert M. Houle , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C8/08
摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.
摘要翻译：在制造的SRAM中设置字线上电压的方法。在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。

35. 发明授权

US07724559B2 Self-referenced match-line sense amplifier for content addressable memories 有权
标题翻译：用于内容可寻址存储器的自参考匹配线检测放大器
公开(公告)号：US07724559B2
公开(公告)日：2010-05-25
申请号：US11457477
申请日：2006-07-14
申请人： Igor Arsovski
发明人： Igor Arsovski
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C7/067 , G11C7/12
摘要： A content addressable memory (CAM) device and process for searching a CAM. The CAM device includes a plurality of CAM cells, match-lines (MLs), search lines, and ML sense amplifiers. The ML sense amplifiers are capable of self-calibration to their respective thresholds to reduce effects of random device variation between adjacent sense amplifiers.
摘要翻译：用于搜索CAM的内容可寻址存储器（CAM）设备和处理。 CAM设备包括多个CAM单元，匹配线（ML），搜索线和ML读出放大器。 ML读出放大器能够对其各自的阈值进行自校准，以减少相邻读出放大器之间的随机器件变化的影响。

36. 发明申请

US20090303820A1 APPARATUS AND METHOD FOR LOW POWER SENSING IN A MULTI-PORT SRAM USING PRE-DISCHARGED BIT LINES 有权
标题翻译：使用预放电位线的多端口SRAM中的低功率感测的装置和方法
公开(公告)号：US20090303820A1
公开(公告)日：2009-12-10
申请号：US12135229
申请日：2008-06-09
申请人： Igor Arsovski , Michael Thomas Fragano , Robert Maurice Houle
发明人： Igor Arsovski , Michael Thomas Fragano , Robert Maurice Houle
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/16 , G11C11/419
摘要： A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different than the zero voltage potential during an access of the memory cell; and sensing the memory cell contents when the associated bit line has reached the first voltage potential.
摘要翻译：一种用于感测静态随机存取存储器（SRAM）内的存储单元的内容的方法包括当存储单元未被访问时，将与存储单元相关联的位线保持在零电压电位; 在存储器单元的访问期间将位线激励到不同于零电压电位的第一电压电位; 以及当相关联的位线已经达到第一电压电位时感测存储器单元的内容。

37. 发明申请

US20090141529A1 DESIGN STRUCTURE FOR IMPLEMENTING MATRIX-BASED SEARCH CAPABILITY IN CONTENT ADDRESSABLE MEMORY DEVICES 有权
标题翻译：在内容可寻址存储器件中实现基于矩阵的搜索能力的设计结构
公开(公告)号：US20090141529A1
公开(公告)日：2009-06-04
申请号：US12110375
申请日：2008-04-28
申请人： Igor Arsovski , Kerry Bernstein
发明人： Igor Arsovski , Kerry Bernstein
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括内容可寻址存储器（CAM）装置，其具有排列成字线方向的存储单元阵列和排列在位线方向上的列，并且配置有比较电路将存储在阵列中的数据与存储在阵列的每一行和列中的数据进行比较，同时在阵列的每一行和列上指示匹配结果，从而产生二维的基于矩阵的数据比较操作。

38. 发明申请

US20080219069A1 DEVICE THRESHOLD CALIBRATION THROUGH STATE DEPENDENT BURNIN 有权
标题翻译：通过状态相关燃烧器进行设备阈值校准
公开(公告)号：US20080219069A1
公开(公告)日：2008-09-11
申请号：US11684225
申请日：2007-03-09
申请人： Igor Arsovski , Harold Pilo , Michael A. Ziegerhofer
发明人： Igor Arsovski , Harold Pilo , Michael A. Ziegerhofer
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/028
摘要： Disclosed are embodiments of a method for reducing and/or eliminating mismatch. The embodiments sample the bias of one or more circuit sub-components that require a balanced state (e.g., sampling the bias of the cross-coupled transistors in each memory cell and/or sense amp in a memory array) before chip burn-in, by initiating a burn-in process during which an individually selected state is applied to each of the devices in the circuit. This fatigues the devices away from their preferred states and towards a balanced state. The bias is periodically reassessed during the burn-in process to avoid over-correction. By using this method both memory cell and sense-amplifier mismatch can be reduced in memory arrays, resulting in smaller timing uncertainty and therefore faster memories.
摘要翻译：公开了用于减少和/或消除错配的方法的实施例。这些实施例在芯片烧录之前对需要平衡状态的一个或多个电路子部件（例如，在每个存储器单元中的交叉耦合晶体管的偏置和/或存储器阵列中的读出放大器）进行采样，通过启动老化过程，在该过程中，单独选择的状态被应用于电路中的每个设备。这使得设备远离其优选的状态并且朝向平衡状态。在老化过程中定期重新评估偏差，以避免过度校正。通过使用这种方法，可以在存储器阵列中减少存储器单元和读出放大器的失配，从而导致较小的定时不确定性，因此更快的存储器。

39. 发明申请

US20080212350A1 CAM Asynchronous Search-Line Switching 失效
公开(公告)号：US20080212350A1
公开(公告)日：2008-09-04
申请号：US12047209
申请日：2008-03-12
申请人： Igor Arsovski
发明人： Igor Arsovski
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C7/02
摘要： This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A reference match-line is provided to generate the timing for the search operation and provide the timing for the asynchronous application of the search data on the SLs. Additional noise reduction is achieved through the staggering of the search data application on the SLs through programmable delay elements

40. 发明申请

US20080030254A1 DESIGN STRUCTURE TO ELIMINATE STEP RESPONSE POWER SUPPLY PERTURBATION 失效
标题翻译：消除步骤响应电源扰动的设计结构
公开(公告)号：US20080030254A1
公开(公告)日：2008-02-07
申请号：US11847362
申请日：2007-08-30
申请人： Igor Arsovski , Joseph Iadanza
发明人： Igor Arsovski , Joseph Iadanza
IPC分类号： H03K17/16
CPC分类号： H03K19/00346 , H03K17/162
摘要： A design structure for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.
摘要翻译：公开了一种用于在集成电路上的电压岛上电/掉电期间消除阶跃响应电源扰动的设计结构。 IC芯片与主电源通信并且包括至少一个电压岛。芯片的电压岛上的主要头部通过主头电源路径与主电源通信。芯片的电压岛上的次级标题通过辅助电源通路与二次电源通信。与IC芯片和电压岛通信的控制解码器调节主集线器和副集线器的状态。

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