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31. 发明申请

US20070284668A1 CMOS S/D SiGe DEVICE MADE WITH ALTERNATIVE INTEGRATION PROCESS 审中-公开
标题翻译： CMOS S / D SiGe器件与替代整合过程
公开(公告)号：US20070284668A1
公开(公告)日：2007-12-13
申请号：US11739103
申请日：2007-04-24
申请人： Meihua Shen , Yonah Cho , Mark Kawaguchi , Faran Nouri , Diana Ma
发明人： Meihua Shen , Yonah Cho , Mark Kawaguchi , Faran Nouri , Diana Ma
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/28044 , H01L21/823807 , H01L29/165 , H01L29/518 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device includes a substrate having regions filled with an additive that forms a source/drain for a MOS device, a gate dielectric layer deposited over the substrate, the gate dielectric layer electrically isolates the substrate from subsequently deposited layers, a gate electrode deposited over the gate dielectric layer, an oxide liner formed along laterally opposite sidewalls of the gate electrode, a nitride layer formed along the oxide liner extending above the gate electrode, and wherein the additive and the nitride layer enclose the gate electrode.
摘要翻译：半导体器件包括具有填充有添加剂的区域的衬底，其形成用于MOS器件的源极/漏极，沉积在衬底上的栅极电介质层，栅极介电层将衬底与随后沉积的层电隔离，栅极电极沉积在栅极电介质层，沿着栅电极的横向相对的侧壁形成的氧化物衬垫，沿着在栅电极上方延伸的氧化物衬垫形成的氮化物层，并且其中添加剂和氮化物层包围栅电极。

32. 发明申请

US20070281479A1 Process including silo-chloro passivation for etching tungsten silicide overlying polysilicon 审中-公开
标题翻译：包括用于蚀刻硅化钨覆盖多晶硅的硅 - 氯钝化的方法
公开(公告)号：US20070281479A1
公开(公告)日：2007-12-06
申请号：US11513455
申请日：2006-08-31
申请人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
发明人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
IPC分类号： C23F1/00 , H01L21/302
CPC分类号： H01L21/32136 , H01L21/32137 , H01L29/40114
摘要： A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 as an example of a silicon and chlorine containing passivating gas may be added for additional selectivity.
摘要翻译：在多晶硅上等离子体蚀刻钨硅化物的方法，特别可用于制造具有密集填充区域和开放（iso）区域的闪存，其需要由于微负载而长时间过蚀刻。在过蚀刻中晶片偏置减小。主要的蚀刻剂包括NF 3和Cl 2。加入氩气以防止在密/异界面处的底切。氧和氮氧化任何暴露的硅以提高蚀刻选择性并矫正蚀刻轮廓。作为含硅和氯的钝化气体的实例，可以加入作为另外选择性的SiCl 4 Si 3。

33. 发明授权

US06566270B1 Integration of silicon etch and chamber cleaning processes 失效
标题翻译：硅蚀刻和室清洁工艺的集成
公开(公告)号：US06566270B1
公开(公告)日：2003-05-20
申请号：US09662677
申请日：2000-09-15
申请人： Wei Liu , Scott Williams , Stephen Yuen , David Mui , Meihua Shen
发明人： Wei Liu , Scott Williams , Stephen Yuen , David Mui , Meihua Shen
IPC分类号： H01L21302
CPC分类号： H01L21/3065
摘要： A method for processing a substrate disposed in a substrate process chamber having a source power includes transferring the substrate into the substrate process chamber. A trench is etched on the substrate by exposing the substrate to a plasma formed from a first etchant gas by applying RF energy from the source power system and biasing the plasma toward the substrate. Byproducts adhering to inner surfaces of the substrate process chamber are removed by igniting a plasma formed from a second etchant gas including a halogen source in the substrate process chamber without applying bias power or applying minimal bias power. Thereafter, the substrate is removed from the chamber. At least 100 more substrates are processed with the etching-a-trench step and removing-etch-byproducts step before performing a dry clean or wet clean operation on the chamber.
摘要翻译：用于处理设置在具有源功率的基板处理室中的基板的方法包括将基板转移到基板处理室中。通过从源功率系统施加RF能量并将等离子体偏压到衬底，将衬底暴露于由第一蚀刻剂气体形成的等离子体上，在衬底上蚀刻沟槽。通过在不施加偏置功率或施加最小偏压功率的情况下点燃由包括卤素源的第二蚀刻剂气体在衬底处理室中形成的等离子体而去除附着于衬底处理室的内表面的副产物。此后，将基板从腔室中取出。在对腔室进行干洗或湿清洁操作之前，至少用100个蚀刻a沟槽步骤和去除蚀刻副产物步骤处理多个衬底。

34. 发明授权

US07718081B2 Techniques for the use of amorphous carbon (APF) for various etch and litho integration schemes 失效
标题翻译：使用无定形碳（APF）进行各种蚀刻和光刻积分方案的技术
公开(公告)号：US07718081B2
公开(公告)日：2010-05-18
申请号：US11422031
申请日：2006-06-02
申请人： Wei Liu , Jim Zhongyi He , Sang H. Ahn , Meihua Shen , Hichem M'Saad , Wendy H. Yeh , Christopher D. Bencher
发明人： Wei Liu , Jim Zhongyi He , Sang H. Ahn , Meihua Shen , Hichem M'Saad , Wendy H. Yeh , Christopher D. Bencher
IPC分类号： C23F1/00 , B44C1/22 , G03C5/00 , H01L21/302 , C03C25/68
CPC分类号： G03F7/091 , H01L21/0276 , H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/3146
摘要： A method of etching a substrate is provided. The method of etching a substrate includes transferring a pattern into the substrate using a double patterned amorphous carbon layer on the substrate as a hardmask. Optionally, a non-carbon based layer is deposited on the amorphous carbon layer as a capping layer before the pattern is transferred into the substrate.
摘要翻译：提供蚀刻基板的方法。蚀刻基板的方法包括使用基板上的双图案化非晶碳层作为硬掩模将图案转印到基板中。任选地，在将图案转移到基底内之前，将非碳基层沉积在无定形碳层上作为覆盖层。

35. 发明申请

US20100018648A1 WORKPIECE SUPPORT FOR A PLASMA REACTOR WITH CONTROLLED APPORTIONMENT OF RF POWER TO A PROCESS KIT RING 审中-公开
标题翻译：用于等离子体反应器的工作支持，具有控制的RF功率分配到工艺套件环
公开(公告)号：US20100018648A1
公开(公告)日：2010-01-28
申请号：US12178032
申请日：2008-07-23
申请人： KENNETH S. COLLINS , Douglas A. Buchberger, JR. , Kartik Ramaswamy , Shahid Rauf , Hiroji Hanawa , Jennifer Y. Sun , Andrew Nguyen , Thorsten B. Lill , Meihua Shen
发明人： KENNETH S. COLLINS , Douglas A. Buchberger, JR. , Kartik Ramaswamy , Shahid Rauf , Hiroji Hanawa , Jennifer Y. Sun , Andrew Nguyen , Thorsten B. Lill , Meihua Shen
IPC分类号： H01L21/3065
CPC分类号： H01J37/32642 , H01J37/32082 , H01J37/32174 , H01J37/32623 , H01J2237/2001 , H01L21/6833
摘要： In an electrostatic chuck, RF bias power is separately applied to a workpiece and to a process kit collar surrounding the workpiece. At least one variable impedance element governed by a system controller adjusts the apportionment of RF bias power between the workpiece and the process kit collar, allowing dynamic adjustment of the plasma sheath electric field at the extreme edge of the workpiece, for optimum electric field uniformity under varying plasma conditions, for example.
摘要翻译：在静电卡盘中，RF偏置功率分别施加到工件和围绕工件的处理套件套环。由系统控制器控制的至少一个可变阻抗元件调节工件和工艺套件套环之间的RF偏置功率的分配，允许动态调整工件最末端处的等离子体护套电场，以获得最佳的电场均匀度改变等离子体条件。

36. 发明申请

US20090061544A1 TRAJECTORY BASED CONTROL OF PLASMA PROCESSING 审中-公开
标题翻译：基于TRAJECTORY的等离子体处理控制
公开(公告)号：US20090061544A1
公开(公告)日：2009-03-05
申请号：US11948030
申请日：2007-11-30
申请人： JOHN P. HOLLAND , John M. Yamartino , Thorsen B. Lill , Meihua Shen , Alexander Paterson , Valentin N. Todorow
发明人： JOHN P. HOLLAND , John M. Yamartino , Thorsen B. Lill , Meihua Shen , Alexander Paterson , Valentin N. Todorow
IPC分类号： H01L21/66 , H01L21/306
CPC分类号： H01L21/32137 , H01J37/32935 , H01J37/3299 , H01L22/26
摘要： A method of controlling a plasma processing according to trajectories connecting start and stop values of parameters controlling the plasma processing, for example, gas flow and power supplied to generate the plasma. The trajectories maybe based on equations including at least time as a variable. At set times within the processing, the values of the parameters are updated according to the predetermined trajectories. Sensors associated with the chamber may also adjust the trajectories, provide variables to the equations, and/or define the trajectories.
摘要翻译：根据控制等离子体处理的参数的启动和停止值的轨迹控制等离子体处理的方法，例如供应的气体流量和功率以产生等离子体。轨迹可以基于包括至少时间作为变量的方程式。在处理期间的设定时间，根据预定的轨迹更新参数的值。与室相关联的传感器还可以调整轨迹，向等式提供变量，和/或定义轨迹。

37. 发明授权

US07368394B2 Etch methods to form anisotropic features for high aspect ratio applications 失效
标题翻译：蚀刻方法来形成高纵横比应用的各向异性特征
公开(公告)号：US07368394B2
公开(公告)日：2008-05-06
申请号：US11363834
申请日：2006-02-27
申请人： Meihua Shen , Uwe Leucke , Guangxiang Jin , Xikun Wang , Wei Liu , Scott Williams
发明人： Meihua Shen , Uwe Leucke , Guangxiang Jin , Xikun Wang , Wei Liu , Scott Williams
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/76802 , H01L21/32137 , H01L21/76814
摘要： Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.
摘要翻译：在本发明中提供了用于在蚀刻工艺中形成用于高纵横比应用的各向异性特征的方法。本文描述的方法通过侧壁钝化管理方案有利地促进具有高纵横比的特征的轮廓和尺寸控制。在一个实施例中，通过在蚀刻层的侧壁和/或底部选择性地形成氧化钝化层来管理侧壁钝化。在另一个实施例中，通过周期性地清除覆盖层再沉积层以在其上保持均匀且均匀的钝化层来管理侧壁钝化。均匀和均匀的钝化允许以在衬底上的高和低特征密度区域中具有临界尺寸的期望深度和垂直分布的方式来逐渐蚀刻具有高纵横比的特征，而不产生缺陷和/或过蚀刻下面层。

38. 发明申请

US20070287244A1 ALTERNATIVE INTEGRATION SCHEME FOR CMOS S/D SiGe PROCESS 审中-公开
标题翻译： CMOS S / D SiGe工艺的替代整合方案
公开(公告)号：US20070287244A1
公开(公告)日：2007-12-13
申请号：US11739099
申请日：2007-04-24
申请人： Meihua Shen , Yonah Cho , Mark Kawaguchi , Faran Nouri , Diana Ma
发明人： Meihua Shen , Yonah Cho , Mark Kawaguchi , Faran Nouri , Diana Ma
IPC分类号： H01L21/8236
CPC分类号： H01L21/823814 , H01L21/823864
摘要： A method for fabricating a semiconductor device with adjacent PMOS and NMOS devices on a substrate includes forming a PMOS gate electrode with a PMOS hardmask on a semiconductor substrate with a PMOS gate dielectric layer in between, forming an NMOS gate electrode with an NMOS hardmask on a semiconductor substrate with an NMOS gate dielectric layer in between, forming an oxide liner over a portion of the PMOS gate electrode and over a portion of the NMOS gate electrode, forming a lightly doped N-Halo implant, depositing a nitride layer over the oxide liner, depositing photoresist on the semiconductor substrate in a pattern that covers the NMOS device, etching the nitride layer from the PMOS device, wherein the etching nitride layer leaves a portion of the nitride layer on the oxide liner, etching semiconductor substrate to form a Si recess, and depositing SiGe into the Si recesses, wherein the SiGe and the nitride layer enclose the oxide liner. The method can also include implanting in the semiconductor substrate a source and drain region for the PMOS.
摘要翻译：一种用于在衬底上制造具有相邻PMOS和NMOS器件的半导体器件的方法包括在半导体衬底上形成具有PMOS硬掩模的PMOS栅电极，其间具有PMOS栅极介电层，在NMOS栅极上形成NMOS栅极半导体衬底，其间具有NMOS栅极介电层，在PMOS栅电极的一部分上方和NMOS栅电极的一部分之上形成氧化物衬垫，形成轻掺杂的N-Halo注入，在氧化物衬垫上沉积氮化物层以覆盖所述NMOS器件的图案沉积在所述半导体衬底上的光致抗蚀剂，从所述PMOS器件蚀刻所述氮化物层，其中所述蚀刻氮化物层离开所述氧化物衬底上的所述氮化物层的一部分，蚀刻半导体衬底以形成Si凹槽并且将SiGe沉积到Si凹部中，其中SiGe和氮化物层包围氧化物衬垫。该方法还可以包括在半导体衬底中注入用于PMOS的源极和漏极区域。

39. 发明授权

US06635573B2 Method of detecting an endpoint during etching of a material within a recess 失效
标题翻译：在蚀刻凹陷内的材料时检测端点的方法
公开(公告)号：US06635573B2
公开(公告)日：2003-10-21
申请号：US10040109
申请日：2001-10-29
申请人： Wilfred Pau , Meihua Shen , Jeffrey D. Chinn
发明人： Wilfred Pau , Meihua Shen , Jeffrey D. Chinn
IPC分类号： H01L21302
CPC分类号： H01L22/26 , H01L21/32137
摘要： We have discovered a method of detecting the approach of an endpoint during the etching of a material within a recess such as a trench or a contact via. The method provides a clear and distinct inflection endpoint signal, even for areas of a substrate containing isolated features. The method includes etching the material in the recess and using thin film interferometric endpoint detection to detect an endpoint of the etch process, where the interferometric incident light beam wavelength is tailored to the material being etched; the spot size of the substrate illuminated by the light beam is sufficient to provide adequate signal intensity from the material being etched; and the refractive index of the material being etched is sufficiently different from the refractive index of other materials contributing to reflected light from the substrate, that the combination of the light beam wavelength, the spot size, and the difference in refractive index provides a clear and distinct endpoint signal.
摘要翻译：我们已经发现了在凹槽（例如沟槽或接触通孔）内蚀刻材料期间检测端点的接近方法。该方法提供清晰和明确的拐点端点信号，即使对于包含隔离特征的基板的区域也是如此。该方法包括蚀刻凹陷中的材料并使用薄膜干涉测量端点检测来检测蚀刻过程的终点，其中干涉入射光束波长适合被蚀刻的材料; 由光束照射的基板的光斑尺寸足以从被蚀刻的材料提供足够的信号强度; 并且被蚀刻的材料的折射率与其他有助于来自衬底的反射光的材料的折射率充分不同，光束波长，光点尺寸和折射率差的组合提供了清晰和不同的端点信号。

40. 发明授权

US06551941B2 Method of forming a notched silicon-containing gate structure 失效
标题翻译：形成缺口含硅栅极结构的方法
公开(公告)号：US06551941B2
公开(公告)日：2003-04-22
申请号：US09791446
申请日：2001-02-22
申请人： Chan-syun David Yang , Meihua Shen , Oranna Yauw , Jeffrey D. Chinn
发明人： Chan-syun David Yang , Meihua Shen , Oranna Yauw , Jeffrey D. Chinn
IPC分类号： H01L2100
CPC分类号： H01L21/32137 , H01L21/28114 , H01L21/28123
摘要： A method of forming a notch silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate layer is etched to a first desired depth using a plasma generated from a first source gas. During the etch, etch byproducts deposit on upper sidewalls of the silicon-containing gate layer which are exposed during etching, forming a first passivation layer which protects the upper silicon-containing gate layer sidewalls from etching during subsequent processing steps. A relatively high substrate bias power is used during this first etch step to ensure that the passivation layer adheres properly to the upper silicon-containing gate sidewalls. The remaining portion of the silicon-containing gate layer is etched at a lower bias power using a plasma generated from a second source gas which selectively etches the silicon-containing gate layer relative to the underlying gate dielectric layer, whereby a lower sidewall of the silicon-containing gate layer is formed and an upper surface of the gate dielectric layer is exposed. The etch stack is then exposed to a plasma generated from a third source gas which includes nitrogen, whereby a second, nitrogen-containing passivation layer is formed on the exposed sidewalls of the silicon-containing gate layer. Subsequently, a notch is etched in the lower sidewall of the silicon-containing gate layer. The method of the invention provides control over both the height and the width of the notch, while providing a marked improvement in notch critical dimension uniformity between isolated and dense feature areas of the substrate.
摘要翻译：公开了一种形成缺口含硅栅极结构的方法。该方法在形成T形含硅栅极结构中特别有用。使用从第一源气体产生的等离子体将含硅栅极层蚀刻到第一期望深度。在蚀刻期间，蚀刻副产物沉积在蚀刻期间暴露的含硅栅极层的上侧壁上，形成第一钝化层，其在随后的处理步骤期间保护上部含硅栅极层侧壁免受蚀刻。在该第一蚀刻步骤期间使用相对较高的衬底偏置功率以确保钝化层适当地粘附到上部含硅栅极侧壁。使用从第二源气体产生的等离子体以较低的偏置功率蚀刻剩余部分的含硅栅极层，该等离子体选择性地相对于下面的栅介质层蚀刻含硅栅极层，由此硅的下侧壁形成栅极层，并且露出栅极电介质层的上表面。然后将蚀刻堆叠暴露于由包括氮的第三源气体产生的等离子体，由此在含硅栅极层的暴露的侧壁上形成第二含氮钝化层。随后，在含硅栅极层的下侧壁蚀刻凹口。本发明的方法提供对凹口的高度和宽度的控制，同时提供了衬底的隔离和致密特征区域之间的切口临界尺寸均匀性的显着改进。

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