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31. 发明申请

US20090080265A1 MULTIPLE BIT LINE VOLTAGES BASED ON DISTANCE 有权
标题翻译：基于距离的多位线路电压
公开(公告)号：US20090080265A1
公开(公告)日：2009-03-26
申请号：US11861571
申请日：2007-09-26
申请人： Nima Mokhlesi , Dengtao Zhao , Man Mui , Hao Nguyen , Seungpil Lee , Deepak Chandra Sekar , Tapan Samaddar
发明人： Nima Mokhlesi , Dengtao Zhao , Man Mui , Hao Nguyen , Seungpil Lee , Deepak Chandra Sekar , Tapan Samaddar
IPC分类号： G11C16/24 , G11C7/12 , G11C16/26
CPC分类号： G11C16/0483 , G11C7/12 , G11C11/5642 , G11C16/24 , G11C16/26 , G11C2211/5634
摘要： An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.
摘要翻译：非易失性存储元件的阵列包括连接到所选字线的第一组非易失性存储元件，连接到所选择的字线的第二组非易失性存储元件，与所选字线连接的第一组位线第一组非易失性存储元件，与第二组非易失性存储元件通信的第二组位线，位于第一位置并连接到第一组位线的第一组感测模块，以及位于第二位置并连接到第二组位线的第二组感测模块。第一组感测模块基于第一组感测模块和第一组非易失性存储元件之间的位线距离来施加第一位线电压。第二组感测模块基于第二组感测模块和第二组非易失性存储元件之间的位线距离来施加第二位线电压。

32. 发明申请

US20090080229A1 SINGLE-LAYER METAL CONDUCTORS WITH MULTIPLE THICKNESSES 有权
标题翻译：单层金属导体与多个厚度
公开(公告)号：US20090080229A1
公开(公告)日：2009-03-26
申请号：US11861994
申请日：2007-09-26
申请人： Deepak Chandra Sekar , Nima Mokhlesi
发明人： Deepak Chandra Sekar , Nima Mokhlesi
IPC分类号： G11C5/06 , H01L21/4763
CPC分类号： G11C16/0483 , H01L21/76807 , H01L21/76816 , H01L21/76817 , H01L23/528 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A pattern that includes trenches of different depths is formed on a substrate using nanoimprint lithography. A subsequent metal deposition forms lines of different thicknesses according to trench depth, from a single metal layer. Vias extending down from lines are also formed from the same layer. Individual bit lines are formed having different thicknesses at different locations.
摘要翻译：使用纳米压印光刻法在衬底上形成包括不同深度的沟槽的图案。随后的金属沉积根据沟槽深度从单个金属层形成不同厚度的线。从线路向下延伸的通道也由同一层形成。在不同位置处形成具有不同厚度的各个位线。

33. 发明授权

US07508710B2 Operating non-volatile memory with boost structures 有权
标题翻译：使用升压结构操作非易失性存储器
公开(公告)号：US07508710B2
公开(公告)日：2009-03-24
申请号：US11558980
申请日：2006-11-13
申请人： Nima Mokhlesi
发明人： Nima Mokhlesi
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A method for operating non-volatile memory having boost structures. The boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or verify level. The boost structures assists in programming so that the programming and pass voltage on a word line can be reduced, thereby reducing side effects such as program disturb. During verifying, all storage elements on a word line can be verified concurrently. The boost structure can also assist during reading. In one approach, the NAND string has dual source-side select gates between which the boost structure contacts the substrate at a source/drain region, and a boost voltage is provided to the boost structure via a source-side of the NAND string.
摘要翻译：一种用于操作具有升压结构的非易失性存储器的方法。为单个NAND串提供升压结构，并且可以单独控制升压结构，以协助编程，验证和读取过程。升压结构可以通常被提升和单独放电，部分地基于目标编程状态或验证电平。升压结构有助于编程，从而可以减少字线上的编程和通过电压，从而减少诸如程序干扰的副作用。在验证期间，可以同时验证字线上的所有存储元素。升压结构也可以在阅读过程中有所帮助。在一种方法中，NAND串具有双源极选择栅极，在该源极/漏极区域之间升压结构与衬底接触，并且经由NAND串的源极侧将升压电压提供给升压结构。

34. 发明授权

US07495962B2 Alternating read mode 有权
标题翻译：交替读取模式
公开(公告)号：US07495962B2
公开(公告)日：2009-02-24
申请号：US11618569
申请日：2006-12-29
申请人： Nima Mokhlesi
发明人： Nima Mokhlesi
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/3418
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storage element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other charge storing elements). To account for this coupling, the read process for a targeted memory cell will provide compensation to an adjacent memory cell (or other memory cell) in order to reduce the coupling effect that the adjacent memory cell has on the targeted memory cell. The compensation applied is based on a condition of the adjacent memory cell. To apply the correct compensation, the read process will at least partially intermix read operations for the adjacent memory cell with read operations for the targeted memory cell.
摘要翻译：由于存储在相邻浮动栅极（或其他电荷存储元件）中的电荷的电场的耦合，可能会发生存储在非易失性存储单元的浮动栅极（或其他电荷存储元件）上的视在电荷的变化，。为了解决这种耦合，对于目标存储器单元的读取处理将向邻近的存储器单元（或其他存储单元）提供补偿，以便减少相邻存储单元对目标存储器单元具有的耦合效应。所施加的补偿基于相邻存储单元的条件。为了应用正确的补偿，读取过程将至少部分地将相邻存储器单元的读取操作与目标存储器单元的读取操作混合。

35. 发明申请

US20080318381A1 METHODS OF FORMING HIGH DENSITY SEMICONDUCTOR DEVICES USING RECURSIVE SPACER TECHNIQUE 有权
标题翻译：使用回放间隔技术形成高密度半导体器件的方法
公开(公告)号：US20080318381A1
公开(公告)日：2008-12-25
申请号：US11765866
申请日：2007-06-20
申请人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
发明人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.
摘要翻译：公开了高密度半导体器件及其制造方法。利用间隔器制造技术来形成具有减小的特征尺寸的电路元件，其可以小于所使用的工艺的最小可光刻解析的元件尺寸。可以处理第一组间隔件以提供平面和平行的侧壁。可以在第一组间隔件的平面和平行的侧壁上形成第二组间隔件。第二组间隔件用作掩模以在第二组间隔物下方的层中形成一个或多个电路元件。根据本发明的实施例的步骤允许使用递归间隔物技术，其产生要形成的坚固的，均匀间隔的间隔物并用作电路元件的掩模。

36. 发明授权

US07468919B2 Biasing non-volatile storage based on selected word line 有权
标题翻译：基于所选字线偏置非易失性存储
公开(公告)号：US07468919B2
公开(公告)日：2008-12-23
申请号：US11618788
申请日：2006-12-30
申请人： Deepak Chandra Sekar , Nima Mokhlesi
发明人： Deepak Chandra Sekar , Nima Mokhlesi
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483
摘要： A body bias is applied to a non-volatile storage system to compensate for performance variations which are based on the position of a selected word line which is associated with non-volatile storage elements undergoing program, read or verify operations. In one approach, the body bias increases when the selected word line is closer to a drain side of a NAND string than a source side. In another approach, the body bias varies when the selected word line is an end word line. In another approach, first or second body bias levels can be used when the selected word line is in a first or second group of word lines, respectively. The body bias reduces variations in threshold voltage levels and threshold voltage distributions which are based on the selected word line position. Gate-induced drain leakage (GIDL) is also reduced.
摘要翻译：身体偏差被施加到非易失性存储系统以补偿基于与经历程序，读取或验证操作的非易失性存储元件相关联的所选字线的位置的性能变化。在一种方法中，当选择的字线比源极侧更靠近NAND串的漏极侧时，体偏置增加。在另一种方法中，当选择的字线是结束字线时，体偏差变化。在另一方法中，当所选择的字线分别在第一或第二组字线组中时，可以使用第一或第二体偏置电平。身体偏置减少了基于所选字线位置的阈值电压电平和阈值电压分布的变化。栅极漏极泄漏（GIDL）也减小。

37. 发明授权

US07450421B2 Data pattern sensitivity compensation using different voltage 有权
标题翻译：使用不同电压的数据模式灵敏度补偿
公开(公告)号：US07450421B2
公开(公告)日：2008-11-11
申请号：US11421871
申请日：2006-06-02
申请人： Nima Mokhlesi , Yingda Dong
发明人： Nima Mokhlesi , Yingda Dong
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： Errors can occur when reading the threshold voltage of a programmed non-volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating gates, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. To account for the back pattern effect, a first voltage is used during a verify operation for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. The combination of these two techniques provides for more accurate storage and retrieval of data.
摘要翻译：由于至少两种机制，读取编程的非易失性存储元件的阈值电压时可能会发生错误：（1）相邻浮动栅极之间的电容耦合和（2）编程后改变通道区域的电导率（称为反向图案影响）。为了考虑相邻浮动栅极之间的耦合，对于特定存储器单元的读取处理将为相邻存储器单元提供补偿，以便减少相邻存储器单元对特定存储器单元具有的耦合效应。为了解决背模式效应，在对已经经过编程操作的未选字线的验证操作期间使用第一电压，并且对未经过编程操作的未选字线使用第二电压。这两种技术的组合提供了更准确的数据存储和检索。

38. 发明申请

US20080250300A1 METHOD FOR DECODING DATA IN NON-VOLATILE STORAGE USING RELIABILITY METRICS BASED ON MULTIPLE READS 有权
标题翻译：基于多项阅读的可靠性量度来解密非易失存储数据的方法
公开(公告)号：US20080250300A1
公开(公告)日：2008-10-09
申请号：US11693649
申请日：2007-03-29
申请人： Nima Mokhlesi , Henry Chin , Dengtao Zhao
发明人： Nima Mokhlesi , Henry Chin , Dengtao Zhao
IPC分类号： G11C7/10 , H03M13/00
CPC分类号： G06F12/00 , G11C11/5642 , G11C16/04 , G11C16/28 , G11C29/00 , G11C29/02 , G11C29/028 , H03M13/11 , H03M13/37
摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge. In another approach, the initial reliability metrics are based on multiple reads. Tables which store the reliability metrics and adjustments based on the sensed states can be prepared before decoding occurs.
摘要翻译：使用迭代概率解码和多次读取操作来解码存储在非易失性存储器中的数据，以实现更高的可靠性。可以使用诸如低密度奇偶校验码的纠错码。在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的读取数据。解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。如果没有发生收敛，例如在设定的时间周期内，再次感测到非易失性存储元件的状态，则调整解码器中的可靠性度量的当前值，并且解码再次尝试收敛。在另一种方法中，初始可靠性度量是基于多次读取。可以在解码发生之前准备存储基于感测状态的可靠性度量和调整的表。

39. 发明申请

US20080247238A1 METHOD FOR SENSING NEGATIVE THRESHOLD VOLTAGES IN NON-VOLATILE STORAGE USING CURRENT SENSING 有权
标题翻译：使用电流感测感知非挥发性储存中的负压阈值电压的方法
公开(公告)号：US20080247238A1
公开(公告)日：2008-10-09
申请号：US11771982
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C16/06 , G11C11/4091
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译：在具有负阈值电压的所选择的非易失性存储元件的非易失性存储装置中执行电流感测。控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

40. 发明申请

US20080244360A1 Non-Volatile Memory with Soft Bit Data Transmission for Error Correction Control 有权
标题翻译：具有软位数据传输的非易失性存储器，用于纠错控制
公开(公告)号：US20080244360A1
公开(公告)日：2008-10-02
申请号：US11694948
申请日：2007-03-31
申请人： Nima Mokhlesi , Henry Chin , Dengtao Zhao
发明人： Nima Mokhlesi , Henry Chin , Dengtao Zhao
IPC分类号： H03M13/03
CPC分类号： H03M13/1111 , G06F11/1068 , G11C11/5642 , H03M13/1102
摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.
摘要翻译：使用迭代概率解码对存储在非易失性存储器中的数据进行解码。可以使用诸如低密度奇偶校验码的纠错码。在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的感测状态。解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。如果解码失败，则从存储器读取软数据位。在接收到硬读取结果之后和在软位操作的每个阶段提供初始可靠性度量值。在一个实施例中，使用软比特比较级的多个子集从存储器读取第二软比特。当在比较级的第二子集读取时，可以基于第一子集数据执行解码。

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