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1. 发明授权

US07606079B2 Reducing power consumption during read operations in non-volatile storage 有权
标题翻译：在非易失性存储器中读取操作期间降低功耗
公开(公告)号：US07606079B2
公开(公告)日：2009-10-20
申请号：US11740091
申请日：2007-04-25
申请人： Deepak Chandra Sekar , Nima Mokhlesi , Hock C. So
发明人： Deepak Chandra Sekar , Nima Mokhlesi , Hock C. So
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C8/08 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C2211/5646
摘要： Power consumption in a non-volatile storage device is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.
摘要翻译：在读取操作期间通过在未选择的字线上提供减小的读取通过电压来减少非易失性存储设备中的功耗。检查在其上正在读取存储元件的所选字线之后的一个或多个未选字线的编程状态，以确定未选择的字线是否包含编程的存储元件。当识别出未编程的字线时，在该字线和在该字线之后的编程顺序中的其它字线提供减小的读通道电压。编程状态可以通过例如存储在字线中的标志来确定，或者通过在最低读取状态下读取字线来确定。被检查的未选择的字线可以在一组字线中预先确定，或者基于所选字线的位置自适应地确定。

2. 发明授权

US07532516B2 Non-volatile storage with current sensing of negative threshold voltages 有权
标题翻译：具有电流检测负阈值电压的非易失性存储器
公开(公告)号：US07532516B2
公开(公告)日：2009-05-12
申请号：US11771987
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译：一种非易失性存储装置，其中对具有负阈值电压的非易失性存储元件执行电流检测。控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

3. 发明申请

US20090080265A1 MULTIPLE BIT LINE VOLTAGES BASED ON DISTANCE 有权
标题翻译：基于距离的多位线路电压
公开(公告)号：US20090080265A1
公开(公告)日：2009-03-26
申请号：US11861571
申请日：2007-09-26
申请人： Nima Mokhlesi , Dengtao Zhao , Man Mui , Hao Nguyen , Seungpil Lee , Deepak Chandra Sekar , Tapan Samaddar
发明人： Nima Mokhlesi , Dengtao Zhao , Man Mui , Hao Nguyen , Seungpil Lee , Deepak Chandra Sekar , Tapan Samaddar
IPC分类号： G11C16/24 , G11C7/12 , G11C16/26
CPC分类号： G11C16/0483 , G11C7/12 , G11C11/5642 , G11C16/24 , G11C16/26 , G11C2211/5634
摘要： An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.
摘要翻译：非易失性存储元件的阵列包括连接到所选字线的第一组非易失性存储元件，连接到所选择的字线的第二组非易失性存储元件，与所选字线连接的第一组位线第一组非易失性存储元件，与第二组非易失性存储元件通信的第二组位线，位于第一位置并连接到第一组位线的第一组感测模块，以及位于第二位置并连接到第二组位线的第二组感测模块。第一组感测模块基于第一组感测模块和第一组非易失性存储元件之间的位线距离来施加第一位线电压。第二组感测模块基于第二组感测模块和第二组非易失性存储元件之间的位线距离来施加第二位线电压。

4. 发明申请

US20090080229A1 SINGLE-LAYER METAL CONDUCTORS WITH MULTIPLE THICKNESSES 有权
标题翻译：单层金属导体与多个厚度
公开(公告)号：US20090080229A1
公开(公告)日：2009-03-26
申请号：US11861994
申请日：2007-09-26
申请人： Deepak Chandra Sekar , Nima Mokhlesi
发明人： Deepak Chandra Sekar , Nima Mokhlesi
IPC分类号： G11C5/06 , H01L21/4763
CPC分类号： G11C16/0483 , H01L21/76807 , H01L21/76816 , H01L21/76817 , H01L23/528 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A pattern that includes trenches of different depths is formed on a substrate using nanoimprint lithography. A subsequent metal deposition forms lines of different thicknesses according to trench depth, from a single metal layer. Vias extending down from lines are also formed from the same layer. Individual bit lines are formed having different thicknesses at different locations.
摘要翻译：使用纳米压印光刻法在衬底上形成包括不同深度的沟槽的图案。随后的金属沉积根据沟槽深度从单个金属层形成不同厚度的线。从线路向下延伸的通道也由同一层形成。在不同位置处形成具有不同厚度的各个位线。

5. 发明授权

US07468919B2 Biasing non-volatile storage based on selected word line 有权
标题翻译：基于所选字线偏置非易失性存储
公开(公告)号：US07468919B2
公开(公告)日：2008-12-23
申请号：US11618788
申请日：2006-12-30
申请人： Deepak Chandra Sekar , Nima Mokhlesi
发明人： Deepak Chandra Sekar , Nima Mokhlesi
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483
摘要： A body bias is applied to a non-volatile storage system to compensate for performance variations which are based on the position of a selected word line which is associated with non-volatile storage elements undergoing program, read or verify operations. In one approach, the body bias increases when the selected word line is closer to a drain side of a NAND string than a source side. In another approach, the body bias varies when the selected word line is an end word line. In another approach, first or second body bias levels can be used when the selected word line is in a first or second group of word lines, respectively. The body bias reduces variations in threshold voltage levels and threshold voltage distributions which are based on the selected word line position. Gate-induced drain leakage (GIDL) is also reduced.
摘要翻译：身体偏差被施加到非易失性存储系统以补偿基于与经历程序，读取或验证操作的非易失性存储元件相关联的所选字线的位置的性能变化。在一种方法中，当选择的字线比源极侧更靠近NAND串的漏极侧时，体偏置增加。在另一种方法中，当选择的字线是结束字线时，体偏差变化。在另一方法中，当所选择的字线分别在第一或第二组字线组中时，可以使用第一或第二体偏置电平。身体偏置减少了基于所选字线位置的阈值电压电平和阈值电压分布的变化。栅极漏极泄漏（GIDL）也减小。

6. 发明申请

US20080247238A1 METHOD FOR SENSING NEGATIVE THRESHOLD VOLTAGES IN NON-VOLATILE STORAGE USING CURRENT SENSING 有权
标题翻译：使用电流感测感知非挥发性储存中的负压阈值电压的方法
公开(公告)号：US20080247238A1
公开(公告)日：2008-10-09
申请号：US11771982
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C16/06 , G11C11/4091
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译：在具有负阈值电压的所选择的非易失性存储元件的非易失性存储装置中执行电流感测。控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

7. 发明申请

US20080158960A1 APPLYING ADAPTIVE BODY BIAS TO NON-VOLATILE STORAGE 有权
标题翻译：将自适应身体应用于非易失性存储
公开(公告)号：US20080158960A1
公开(公告)日：2008-07-03
申请号：US11618791
申请日：2006-12-30
申请人： Deepak Chandra Sekar , Nima Mokhlesi
发明人： Deepak Chandra Sekar , Nima Mokhlesi
IPC分类号： G11C29/00
CPC分类号： G11C5/146 , G11C16/10 , G11C16/26 , G11C2029/0409
摘要： Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.
摘要翻译：可以应用身体偏差来优化非易失性存储系统中的性能。当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。此外，随着编程周期的增加，体偏置电平可以增加或减小。此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。

8. 发明授权

US08164957B2 Reducing energy consumption when applying body bias to substrate having sets of nand strings 有权
标题翻译：当将体偏置施加到具有一组n和弦的衬底时，降低能量消耗
公开(公告)号：US08164957B2
公开(公告)日：2012-04-24
申请号：US13178853
申请日：2011-07-08
申请人： Deepak Chandra Sekar , Nima Mokhlesi
发明人： Deepak Chandra Sekar , Nima Mokhlesi
IPC分类号： G11C16/04
CPC分类号： G11C5/146 , G11C16/10 , G11C16/26 , G11C2029/0409
摘要： Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.
摘要翻译：可以应用身体偏差来优化非易失性存储系统中的性能。当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。此外，随着编程周期的增加，体偏置电平可以增加或减小。此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。

9. 发明授权

US07525843B2 Non-volatile storage with adaptive body bias 有权
标题翻译：具有适应性偏置的非易失性存储
公开(公告)号：US07525843B2
公开(公告)日：2009-04-28
申请号：US11618793
申请日：2006-12-30
申请人： Deepak Chandra Sekar , Nima Mokhlesi
发明人： Deepak Chandra Sekar , Nima Mokhlesi
IPC分类号： G11C16/00
CPC分类号： G11C16/28 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C2211/565
摘要： A non-volatile storage system in which body bias can be applied to optimize performance. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.
摘要翻译：可以应用身体偏差以优化性能的非易失性存储系统。当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。此外，随着编程周期的增加，体偏置电平可以增加。此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。

10. 发明申请

US20080158992A1 NON-VOLATILE STORAGE WITH ADAPTIVE BODY BIAS 有权
标题翻译：具有自适应身体偏倚的非挥发性储存
公开(公告)号：US20080158992A1
公开(公告)日：2008-07-03
申请号：US11618793
申请日：2006-12-30
申请人： Deepak Chandra Sekar , Nima Mokhlesi
发明人： Deepak Chandra Sekar , Nima Mokhlesi
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C2211/565
摘要： A non-volatile storage system in which body bias can be applied to optimize performance. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.
摘要翻译：可以应用身体偏差以优化性能的非易失性存储系统。当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。此外，随着编程周期的增加，体偏置电平可以增加。此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。

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