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31. 发明授权

US07581121B2 System for a memory device having a power down mode and method 有权
标题翻译：具有断电模式和方法的存储器件的系统
公开(公告)号：US07581121B2
公开(公告)日：2009-08-25
申请号：US11151791
申请日：2005-06-14
申请人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
发明人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
IPC分类号： G06F1/00 , G06F13/00
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.
摘要翻译：一种系统，包括存储位置以存储表示随机存取存储器件的定时参数的信息。集成电路装置生成代表在从断电模式退出的随机存取存储装置与随机存取存储装置能够接收指令的时间之间经过的时间段的值。集成电路装置根据表示随机存取存储装置的定时参数的信息生成该值。

32. 发明授权

US07529141B2 Asynchronous, high-bandwidth memory component using calibrated timing elements 失效
标题翻译：异步高带宽内存组件使用校准的时序元素
公开(公告)号：US07529141B2
公开(公告)日：2009-05-05
申请号：US12041594
申请日：2008-03-03
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
摘要翻译：这里公开了使用内部延迟元件来启用存储器访问流水线的异步存储器件的实施例。在一个实施例中，延迟元件响应于输入负载控制信号，并且参考周期性接收的定时脉冲进行校准。不同数量的延迟元件被配置为产生不同的异步延迟并选择存储器件的顺序流水线元件。

33. 发明授权

US07225311B2 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
标题翻译：用于在不同位置的存储器组件之间协调存储器操作的方法和装置
公开(公告)号：US07225311B2
公开(公告)日：2007-05-29
申请号：US10732533
申请日：2003-12-11
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F13/00
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset such that the first data arrives at a first memory device in accordance with a predetermined timing relationship with respect to a first transition of the clock signal, and a third transmitter to output second data using a second timing offset such that the second data arrives at a second memory device in accordance with a predetermined timing relationship with respect to a second transition of the clock signal.
摘要翻译：公开了一种存储器控制器。在一个特定的示例性实施例中，存储器控制器可以包括：第一发射器，用于相对于时钟信号同步地输出第一和第二写入命令;第二发射器，使用第一定时偏移来输出第一数据，使得第一数据到达第一根据与时钟信号的第一次转换相关的预定定时关系，以及第三发送器，使用第二定时偏移来输出第二数据，使得第二数据根据预定定时到达第二存储器装置关于时钟信号的第二转换。

34. 发明授权

US07225292B2 Memory module with termination component 有权
标题翻译：具有终端组件的内存模块
公开(公告)号：US07225292B2
公开(公告)日：2007-05-29
申请号：US11219096
申请日：2005-09-01
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F12/00
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory module having a termination component. The memory module includes multiple memory devices, a termination component, a control signal path and multiple data signal paths. The control signal path is coupled to each of the memory devices and the termination component, and extends along the memory devices such that signals propagating on the control signal path propagate past each of the memory devices in succession before reaching the termination component. A unique set of data signal paths is coupled to each of the memory devices.
摘要翻译：一种具有端接部件的存储器模块。存储器模块包括多个存储器件，终端元件，控制信号路径和多个数据信号路径。控制信号路径被耦合到每个存储器件和终端元件，并且沿着存储器件延伸，使得在控制信号路径上传播的信号在到达终端元件之前连续传播通过每个存储器件。一组唯一的数据信号路径耦合到每个存储器件。

35. 发明授权

US07210016B2 Method, system and memory controller utilizing adjustable write data delay settings 有权
标题翻译：方法，系统和内存控制器利用可调写入数据延迟设置
公开(公告)号：US07210016B2
公开(公告)日：2007-04-24
申请号：US11281184
申请日：2005-11-15
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F13/20
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data transmit circuitry transmits data signals to the memory devices via respective data signal paths. The timing circuitry delays transmission of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.
摘要翻译：一种使用可调写入数据延迟设置的方法，系统和存储器控制器。存储器控制器包括控制发射电路，数据发射电路和定时电路。控制电路通过共享控制信号路径将控制信号发送到多个存储器件。数据发送电路经由各自的数据信号路径向存储器件发送数据信号。定时电路延迟每个数据信号路径上的数据信号的传输相应的时间间隔，该时间间隔至少部分地基于控制信号在从存储器控制器到控制信号路径的传播所需的时间相应的一个存储器件。

36. 发明授权

US07073035B2 Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules 有权
标题翻译：增加具有不匹配内存模块的每个模块内存系统带宽的技术
公开(公告)号：US07073035B2
公开(公告)日：2006-07-04
申请号：US11100386
申请日：2005-04-07
申请人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel , Ely K. Tsern
发明人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel , Ely K. Tsern
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G11C8/16
摘要： Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory controller for controlling access to a memory module, wherein the memory module has a memory component with a memory core for storing data therein. The memory controller comprises a first set of interface connections for providing access to the memory module, and a second set of interface connections for providing access to the memory module. The memory controller also comprises memory access circuitry for providing memory access signals to the memory module for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.
摘要翻译：公开了用于增加具有不匹配的存储器模块的每模块模块存储器系统中的带宽的技术。在一个示例性实施例中，通过用于控制对存储器模块的访问的存储器控制器来实现这些技术，其中存储器模块具有存储器组件，存储器组件具有用于在其中存储数据的存储器核心。存储器控制器包括用于提供对存储器模块的访问的第一组接口连接和用于提供对存储器模块的访问的第二组接口连接。存储器控制器还包括用于向存储器模块提供存储器访问信号的存储器访问电路，用于在第一模式之间进行选择，其中存储器核心的第一部分可通过第一组接口连接访问，并且存储器核心的第二部分可访问通过第二组接口连接，以及第二模式，其中存储器核心的第一部分和第二部分都可通过第一组接口连接来访问。

37. 发明授权

US06769050B1 Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules 有权
标题翻译：增加具有不匹配内存模块的每个模块内存系统带宽的技术
公开(公告)号：US06769050B1
公开(公告)日：2004-07-27
申请号：US09948906
申请日：2001-09-10
申请人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel , Ely K. Tsern
发明人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel , Ely K. Tsern
IPC分类号： G06F1200
CPC分类号： G06F13/1684 , G11C8/16
摘要： Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory controller for controlling access to a memory module, wherein the memory module has a memory component with a memory core for storing data therein. The memory controller comprises a first set of interface connections for providing access to the memory module, and a second set of interface connections for providing access to the memory module. The memory controller also comprises memory access circuitry for providing memory access signals to the memory module for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.
摘要翻译：公开了用于增加具有不匹配的存储器模块的每模块模块存储器系统中的带宽的技术。在一个示例性实施例中，通过用于控制对存储器模块的访问的存储器控制器来实现这些技术，其中存储器模块具有存储器组件，存储器组件具有用于在其中存储数据的存储器核心。存储器控制器包括用于提供对存储器模块的访问的第一组接口连接和用于提供对存储器模块的访问的第二组接口连接。存储器控制器还包括用于向存储器模块提供存储器访问信号的存储器访问电路，用于在第一模式之间进行选择，其中存储器核心的第一部分可通过第一组接口连接访问，并且存储器核心的第二部分可访问通过第二组接口连接，以及第二模式，其中存储器核心的第一部分和第二部分都可通过第一组接口连接来访问。

38. 发明授权

US06356975B1 Apparatus and method for pipelined memory operations 失效
公开(公告)号：US06356975B1
公开(公告)日：2002-03-12
申请号：US09169526
申请日：1998-10-09
申请人： Richard M. Barth , Ely K. Tsern , Mark A. Horowitz , Donald C. Stark , Craig E. Hampel , Frederick A. Ware , John B. Dillon , by Nancy David Dillon
发明人： Richard M. Barth , Ely K. Tsern , Mark A. Horowitz , Donald C. Stark , Craig E. Hampel , Frederick A. Ware , John B. Dillon , by Nancy David Dillon
IPC分类号： G06F1200
CPC分类号： G11C7/1006 , G06F13/1615 , G11C7/10 , G11C7/1039 , G11C8/12 , G11C11/4076
摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

39. 发明授权

US09257159B2 Low power memory device 有权
标题翻译：低功耗存储设备
公开(公告)号：US09257159B2
公开(公告)日：2016-02-09
申请号：US14173724
申请日：2014-02-05
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G11C8/00 , G11C7/10 , G11C5/14 , G11C7/22 , G11C8/08 , G11C8/12 , G11C11/4076 , G11C11/408 , G11C11/4063
CPC分类号： G11C7/1006 , G11C5/14 , G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C8/08 , G11C8/12 , G11C11/4063 , G11C11/4076 , G11C11/4085 , G11C2207/2227
摘要： A method of operation within a memory device is disclosed. The method comprises receiving address information and corresponding enable information in association with a memory access request. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The method involves selectively transferring data between the first and second storage locations and sense amplifier circuitry according to states of the first and second enable values. This includes transferring data between the first storage location and the sense amplifier circuitry if the first enable value is in an enable state and transferring data between the second storage location and the sense amplifier circuitry if the second enable value is in the enable state. The states of the first and second enable values may be separately controlled.
摘要翻译：公开了一种存储器件内的操作方法。该方法包括与存储器访问请求相关联地接收地址信息和相应的使能信息。地址信息包括指定存储器件的存储阵列内的存储单元行的行地址，并且使能信息包括分别对应于存储单元行内的第一和第二存储位置的第一和第二使能值。该方法涉及根据第一和第二使能值的状态选择性地在第一和第二存储位置之间传输数据和感测放大器电路。这包括如果第一使能值处于使能状态，则在第一存储位置和读出放大器电路之间传送数据，并且如果第二使能值处于使能状态，则在第二存储位置和读出放大器电路之间传送数据。可以单独控制第一和第二使能值的状态。

40. 发明授权

US08412906B2 Memory apparatus supporting multiple width configurations 有权
标题翻译：支持多种宽度配置的内存设备
公开(公告)号：US08412906B2
公开(公告)日：2013-04-02
申请号：US13365890
申请日：2012-02-03
申请人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.
摘要翻译：描述了组织在存储器子部分中并且包括可配置路由以支持多个数据宽度配置的存储器设备。相对窄的宽度配置加载较少的读出放大器，导致相对较窄的存储器配置的功率消耗减少。还描述了将宽度选择信息传送到可配置的存储装置并支持多个宽度配置的点对点数据接口的存储器控制器。

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