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1. 发明授权

US08756395B2 Controlling DRAM at time DRAM ready to receive command when exiting power down 有权
标题翻译：在DRAM时刻控制DRAM，准备在断电时接收命令
公开(公告)号：US08756395B2
公开(公告)日：2014-06-17
申请号：US13406465
申请日：2012-02-27
申请人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
发明人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
IPC分类号： G06F13/00
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.
摘要翻译：在实施例中提供了存储器件和系统的操作方法。初始化操作在初始化序列期间以第一操作频率进行。然后在第二操作频率下执行存储器存取操作。第二个操作频率高于第一个操作频率。此外，存储器访问操作包括读取操作和写入操作。在实施例中，从串行存在检测装置读取表示第一操作频率和第二操作频率的信息。

2. 发明授权

US08320202B2 Clocked memory system with termination component 有权
标题翻译：带终端组件的定时存储系统
公开(公告)号：US08320202B2
公开(公告)日：2012-11-27
申请号：US11767983
申请日：2007-06-25
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C5/04 , G11C5/063 , G11C7/1048
摘要： A memory system having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data, associated with a write command, to the first memory device, and a second signal line coupled to the second memory device to provide second data, associated with the write command, to the second memory device. A control signal path is coupled to the first and second memory devices and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component. A third signal line is provided to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first and second memory devices.
摘要翻译：一种具有第一和第二存储器件和终端部件的存储器系统。第一信号线耦合到第一存储器设备，以向第一存储器设备提供与写命令相关联的第一数据，以及耦合到第二存储器设备以提供与写命令相关联的第二数据的第二信号线，到第二存储设备。控制信号路径被耦合到第一和第二存储器件和终端部件，使得在到达终端部件之前，在控制信号路径上传播的写入命令传播通过第一存储器件和第二存储器件。提供第三信号线来传送时钟信号，该时钟信号指示在控制信号路径上传播的写入命令何时被第一和第二存储器件采样。

3. 发明申请

US20100061047A1 Upgradable Memory System with Reconfigurable Interconnect 有权
标题翻译：可重构互连的可升级内存系统
公开(公告)号：US20100061047A1
公开(公告)日：2010-03-11
申请号：US12538613
申请日：2009-08-10
申请人： Richard E. Perego , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E. Perego , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F1/16
CPC分类号： G06F13/409 , G11C5/04 , G11C2207/105 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14 , Y02D10/151
摘要： Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.
摘要翻译：描述的是采用可配置的片上终端元件的系统，其允许用户从两个或多个端接拓扑中进行选择。一个拓扑结构可编程，以支持轨到轨或半电源终端。另一种拓扑选择性地包括固定或可变滤波器元件，从而允许针对不同级别的速度性能和功耗来调整终端特性。终端电压和阻抗也可能会被调整。

4. 发明授权

US06934201B2 Asynchronous, high-bandwidth memory component using calibrated timing elements 失效
公开(公告)号：US06934201B2
公开(公告)日：2005-08-23
申请号：US10846220
申请日：2004-05-14
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C7/10 , G11C8/00 , G11C29/02 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.

5. 发明授权

US06842864B1 Method and apparatus for configuring access times of memory devices 失效
标题翻译：用于配置存储设备的访问时间的方法和装置
公开(公告)号：US06842864B1
公开(公告)日：2005-01-11
申请号：US09685014
申请日：2000-10-05
申请人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
发明人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G06F13/00
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.
摘要翻译：提供了用于初始化动态随机存取存储器（DRAM）装置的方法和装置，其中通过确定耦合到总线的多个DRAM装置中的每一个的响应时间来对信道进行均衡化。确定DRAM设备的响应时间包括使用总线将逻辑1写入DRAM设备的存储器位置。随后，通过总线发出读命令，其中读指令寻址到DRAM设备的新写存储位置。然后，存储器控制器测量读取命令的发出和从DRAM设备接收的逻辑电路之间的经过时间，并且该经过时间是DRAM设备的响应时间。在确定每个DRAM器件的响应时间并使用最长的响应时间之后，为耦合到总线的每个DRAM器件计算延迟，使得每个DRAM器件的时钟周期中的响应时间被耦合总线等于最长响应时间。通过将值写入至每个DRAM器件的至少一个寄存器，在连接到总线的每个DRAM器件的至少一个寄存器中编程延迟。

6. 发明授权

US06826657B1 Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules 有权
标题翻译：增加具有不匹配内存模块的每个模块内存系统带宽的技术
公开(公告)号：US06826657B1
公开(公告)日：2004-11-30
申请号：US09948769
申请日：2001-09-10
申请人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel , Ely K. Tsern
发明人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel , Ely K. Tsern
IPC分类号： G06F1200
CPC分类号： G06F13/1684
摘要： Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory system comprising a memory module and a memory controller. The memory module comprises a memory component having a memory core for storing data therein, a first set of interface connections for providing access to the memory core, and a second set of interface connections for providing access to the memory core. The memory module also comprises access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections. The memory controller provides memory access signals to the memory module for selecting between the first mode and the second mode.
摘要翻译：公开了用于增加具有不匹配的存储器模块的每模块模块存储器系统中的带宽的技术。在一个示例性实施例中，通过包括存储器模块和存储器控制器的存储器系统来实现这些技术。存储器模块包括具有用于在其中存储数据的存储器核心的存储器组件，用于提供对存储器核心的访问的第一组接口连接以及用于提供对存储器核心的访问的第二组接口连接。存储器模块还包括访问电路，用于在第一模式之间进行选择，其中存储器核心的第一部分可通过第一组接口连接访问，并且存储器核心的第二部分可通过第二组接口连接访问，并且第二模式，其中存储器核心的第一部分和第二部分都可通过第一组接口连接访问。存储器控制器向存储器模块提供存储器访问信号，用于在第一模式和第二模式之间进行选择。

7. 发明授权

US06788593B2 Asynchronous, high-bandwidth memory component using calibrated timing elements 失效
标题翻译：异步高带宽内存组件使用校准的时序元素
公开(公告)号：US06788593B2
公开(公告)日：2004-09-07
申请号：US09796924
申请日：2001-02-28
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C700
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
摘要翻译：这里公开了使用内部延迟元件来启用存储器访问流水线的异步存储器件的实施例。在一个实施例中，延迟元件响应于输入负载控制信号，并且参考周期性接收的定时脉冲进行校准。不同数量的延迟元件被配置为产生不同的异步延迟并选择存储器件的顺序流水线元件。

8. 发明申请

US20140334238A1 Low Power Memory Device 有权
标题翻译：低功耗存储器件
公开(公告)号：US20140334238A1
公开(公告)日：2014-11-13
申请号：US14173724
申请日：2014-02-05
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G11C7/10 , G11C11/4063 , G11C8/12
CPC分类号： G11C7/1006 , G11C5/14 , G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C8/08 , G11C8/12 , G11C11/4063 , G11C11/4076 , G11C11/4085 , G11C2207/2227
摘要： A method of operation within a memory device is disclosed. The method comprises receiving address information and corresponding enable information in association with a memory access request. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The method involves selectively transferring data between the first and second storage locations and sense amplifier circuitry according to states of the first and second enable values. This includes transferring data between the first storage location and the sense amplifier circuitry if the first enable value is in an enable state and transferring data between the second storage location and the sense amplifier circuitry if the second enable value is in the enable state. The states of the first and second enable values may be separately controlled.
摘要翻译：公开了一种存储器件内的操作方法。该方法包括与存储器访问请求相关联地接收地址信息和相应的使能信息。地址信息包括指定存储器件的存储阵列内的存储单元行的行地址，并且使能信息包括分别对应于存储单元行内的第一和第二存储位置的第一和第二使能值。该方法涉及根据第一和第二使能值的状态选择性地在第一和第二存储位置之间传输数据和感测放大器电路。这包括如果第一使能值处于使能状态，则在第一存储位置和读出放大器电路之间传送数据，并且如果第二使能值处于使能状态，则在第二存储位置和读出放大器电路之间传送数据。可以单独控制第一和第二使能值的状态。

9. 发明授权

US08462566B2 Memory module with termination component 有权
标题翻译：具有终端组件的内存模块
公开(公告)号：US08462566B2
公开(公告)日：2013-06-11
申请号：US12111816
申请日：2008-04-29
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.
摘要翻译：一种具有第一和第二接口的存储器组件。提供第一接口以响应于第一时钟信号对地址信息进行采样。第一接口包括在第一时钟信号的时钟周期期间连续地采样地址信息的至少两个比特的输入。提供第二接口以响应于第二时钟信号采样数据，其具有至少是第一时钟信号频率的两倍的频率。第二接口包括在第二时钟信号的时钟周期期间连续采样至少两位数据的输入。

10. 发明授权

US08391039B2 Memory module with termination component 有权
标题翻译：具有终端组件的内存模块
公开(公告)号：US08391039B2
公开(公告)日：2013-03-05
申请号：US11280560
申请日：2005-11-15
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C5/02
CPC分类号： G11C7/1039 , G11C5/04 , G11C5/063 , G11C7/1048
摘要： A module having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data thereto, the first data to be stored in a memory array of the first memory device during a write operation. A second signal line is coupled to the second memory device to provide thereto, the second data to be stored in a memory array of the second memory device during the write operation. A control signal path is coupled to the first memory device, the second memory device and the termination component such that a write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the first termination component, wherein the write command specifies the write operation.
摘要翻译：具有第一和第二存储器件和终端部件的模块。第一信号线耦合到第一存储器件，以在写入操作期间向第一存储器件提供第一数据以存储在第一存储器件的存储器阵列中。第二信号线耦合到第二存储器设备以在写入操作期间提供要存储在第二存储器件的存储器阵列中的第二数据。控制信号路径被耦合到第一存储器件，第二存储器件和终端元件，使得在到达第一端接元件之前，在控制信号路径上传播的写入命令经过第一存储器件和第二存储器件传播，其中 write命令指定写入操作。

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