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31. 发明申请

US20100133691A1 THERMALLY PROGRAMMABLE ANTI-REVERSE ENGINEERING INTERCONNECTS AND METHODS OF FABRICATING SAME 有权
标题翻译：可逆编程的反向工程互连及其制造方法
公开(公告)号：US20100133691A1
公开(公告)日：2010-06-03
申请号：US12698189
申请日：2010-02-02
申请人： Fen Chen , Cathryn Jeanne Christiansen , Michael Anthony Shinosky , Timothy Dooling Sullivan
发明人： Fen Chen , Cathryn Jeanne Christiansen , Michael Anthony Shinosky , Timothy Dooling Sullivan
IPC分类号： H01L23/50
CPC分类号： H01L21/76895 , H01L23/34 , H01L23/522 , H01L23/576 , H01L2924/0002 , Y10S438/917 , H01L2924/00
摘要： An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.
摘要翻译：互连和互连方法。该方法包括在基底上形成电介质层，介电层具有顶表面和底表面; 在所述电介质层中形成第一线和第二线，所述第一线与所述第二线分离，通过所述介电层的区域; 并且在第一和第二布线之间的电介质层的顶表面中或上方形成金属纳米颗粒，仅在将纳米颗粒加热到大于室温的温度时能够电连接第一布线和第二布线的金属纳米颗粒，在第一和第二导线之间施加电压。

32. 发明申请

US20090107220A1 Design Structure for an On-Chip Real-Time Moisture Sensor For and Method of Detecting Moisture Ingress in an Integrated Circuit Chip 失效
标题翻译：片上实时湿度传感器的设计结构和检测集成电路芯片中水分入口的方法
公开(公告)号：US20090107220A1
公开(公告)日：2009-04-30
申请号：US11926241
申请日：2007-10-29
申请人： Fen Chen , Kai D. Feng
发明人： Fen Chen , Kai D. Feng
IPC分类号： G01N25/56
CPC分类号： G01N27/223
摘要： A design structure for an on-chip real-time moisture detection circuitry for monitoring ingress of moisture into an integrated circuit chip during the operational lifetime of the chip. The moisture detection circuitry includes one or more moisture-sensing units and a common moisture monitor for monitoring the state of each moisture-sensing units. The moisture monitor can be configured to provided a real-time moisture-detected signal for signaling that moisture ingress into the integrated circuit chip has occurred.
摘要翻译：一种片上实时水分检测电路的设计结构，用于在芯片的使用寿命期间监测水分进入集成电路芯片的情况。湿度检测电路包括一个或多个湿度感测单元和用于监测每个湿度感测单元的状态的公共湿度监视器。水分监测器可以被配置为提供实时湿度检测信号，用于发信号通知已经发生湿气进入集成电路芯片。

33. 发明授权

US07500208B2 Non-destructive evaluation of microstructure and interface roughness of electrically conducting lines in semiconductor integrated circuits in deep sub-micron regime 有权
标题翻译：在深亚微米体系的半导体集成电路中的导电线的微结构和界面粗糙度的非破坏性评估
公开(公告)号：US07500208B2
公开(公告)日：2009-03-03
申请号：US11673369
申请日：2007-02-09
申请人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
IPC分类号： G06F17/50 , G01R31/26
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.
摘要翻译：用于评估半导体集成电路中的线路的新型结构和方法。在每个包括多个线段的晶片上形成第一组多条线。所有线段长度相同。测量线路段的电阻。然后，基于所有部分的电阻来确定第一行几何调整。第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。相同长度和厚度的第二组多条线可以形成在同一晶片上。然后，基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

34. 发明申请

US20080232159A1 PHASE-CHANGE TaN RESISTOR BASED TRIPLE-STATE/MULTI-STATE READ ONLY MEMORY 有权
公开(公告)号：US20080232159A1
公开(公告)日：2008-09-25
申请号：US12109081
申请日：2008-04-24
申请人： John M. Aitken , Fen Chen , Kai D. Feng
发明人： John M. Aitken , Fen Chen , Kai D. Feng
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C11/5692 , G11C13/0004 , G11C17/16 , G11C17/18 , H01L27/101 , H01L27/2409 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/145
摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

35. 发明授权

US07345503B2 Method and apparatus for impedance matching in transmission circuits using tantalum nitride resistor devices 有权
标题翻译：使用氮化钽电阻器件的传输电路中的阻抗匹配的方法和装置
公开(公告)号：US07345503B2
公开(公告)日：2008-03-18
申请号：US11427798
申请日：2006-06-30
申请人： Fen Chen , Kai D. Feng , Robert J. Gauthier, Jr. , Tom C. Lee
发明人： Fen Chen , Kai D. Feng , Robert J. Gauthier, Jr. , Tom C. Lee
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/018571
摘要： A method for trimming impedance matching devices in high-speed circuits includes determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test, and comparing the determined electrical parameter associated with the first TaN resistor to a desired design value of the electrical parameter. The resistance value of the first TaN resistor is altered by application of a trimming voltage thereto, wherein the trimming voltage is based on a voltage-resistance characteristic curve of the first TaN resistor. It is then determined whether the altered resistance value of the first TaN resistor causes the electrical parameter to equal the desired design value thereof, and the altering of the resistance value of the first TaN resistor by application of a trimming voltage is repeated until the electrical parameter equals the desired design value thereof.
摘要翻译：一种用于微调高速电路中的阻抗匹配装置的方法包括：确定与在被测电路中用作阻抗匹配装置的第一氮化钽（TaN）电阻相关联的电参数，并将确定的与第一TaN相关的电参数进行比较电阻到所需的电参数设计值。通过施加微调电压来改变第一TaN电阻器的电阻值，其中微调电压基于第一TaN电阻器的耐电压特性曲线。然后确定第一TaN电阻器的改变的电阻值是否使电参数等于其期望的设计值，并且重复通过施加微调电压来改变第一TaN电阻器的电阻值，直到电参数等于其期望的设计值。

36. 发明授权

US08563336B2 Method for forming thin film resistor and terminal bond pad simultaneously 有权
标题翻译：同时形成薄膜电阻和端子焊盘的方法
公开(公告)号：US08563336B2
公开(公告)日：2013-10-22
申请号：US12342430
申请日：2008-12-23
申请人： Fen Chen , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , John C. Malinowski , Anthony K. Stamper
发明人： Fen Chen , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , John C. Malinowski , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： H01L28/20 , H01C7/006 , H01C17/075 , H01L21/7685 , H01L23/5228 , H01L23/53295 , H01L24/11 , H01L28/24 , H01L2224/0231 , H01L2224/02313 , H01L2224/0401 , H01L2224/04042 , H01L2224/05181 , H01L2224/05546 , H01L2224/05624 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01016 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19043 , H01L2924/00014 , H01L2924/013
摘要： Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.
摘要翻译：公开了同时形成薄膜电阻器和端子接合焊盘的方法。一种方法包括在端子线上同时形成端子接合焊盘和在另外两条导线上形成薄膜电阻器。

37. 发明申请

US20130106452A1 REAL-TIME ON-CHIP EM PERFORMANCE MONITORING 有权
标题翻译：实时片上EM性能监控
公开(公告)号：US20130106452A1
公开(公告)日：2013-05-02
申请号：US13282090
申请日：2011-10-26
申请人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
发明人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
IPC分类号： G01R31/3187
CPC分类号： G01R31/3004
摘要： An integrated circuit, testing structure, and method for monitoring electro-migration (EM) performance. A method is described that includes method for measuring on-chip electro-migration (EM) performance, including: providing a first on-chip sensor continuously powered with a stress current; providing a second on-chip sensor that is powered only during measurement cycles with a nominal current; obtaining a first resistance measurement from the first on-chip sensor and a second resistance measurement from the second on-chip sensor during each of a series of measurement cycles; and processing the first and second resistance measurements.
摘要翻译：用于监测电迁移（EM）性能的集成电路，测试结构和方法。描述了一种包括用于测量片上电迁移（EM）性能的方法的方法，包括：提供用应力电流连续供电的第一片上传感器; 提供仅在具有额定电流的测量周期期间供电的第二片上传感器; 在一系列测量周期中的每一个期间，从第一片上传感器获得第一电阻测量值和来自第二片上传感器的第二电阻测量值; 并处理第一和第二电阻测量。

38. 发明授权

US08178434B2 On-chip embedded thermal antenna for chip cooling 有权
标题翻译：片上嵌入式热天线芯片散热
公开(公告)号：US08178434B2
公开(公告)日：2012-05-15
申请号：US13244998
申请日：2011-09-26
申请人： Fen Chen , Jeffrey P. Gambino , Alvin W. Strong
发明人： Fen Chen , Jeffrey P. Gambino , Alvin W. Strong
IPC分类号： H01L21/768
CPC分类号： H01L23/585 , H01L23/3677 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.
摘要翻译：一种装置包括半导体芯片内的第一层，其具有与其它有源结构电连接并且具有电隔离的第一无效结构的有源结构。半导体芯片内的第二层物理连接到第一层。第二层包括绝缘体并具有第二非活性结构。第一非活性结构与第二非活性结构物理对准。

39. 发明申请

US20120080771A1 3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY 有权
标题翻译：具有改进可靠性的浮动导电板的3D VIA电容器
公开(公告)号：US20120080771A1
公开(公告)日：2012-04-05
申请号：US12898340
申请日：2010-10-05
申请人： Chih-Chao Yang , Fen Chen , Baozhen Li
发明人： Chih-Chao Yang , Fen Chen , Baozhen Li
IPC分类号： H01L27/08 , H01L21/02
CPC分类号： H01L23/5223 , H01L21/76805 , H01L25/0657 , H01L28/91 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.
摘要翻译：本发明提供一种3D通孔电容器及其形成方法。电容器包括在基板上的绝缘层。绝缘层具有通孔，其具有侧壁和底部。第一电极覆盖通孔的侧壁和底部的至少一部分。第一高k电介质材料层覆盖在第一电极上。第一导电板在第一高k电介质材料层之上。第二高k电介质材料层覆盖在第一导电板上并留下未填充的通孔的剩余部分。在通孔的剩余部分中形成第二电极。第一导电板基本上平行于第一电极并且不与第一和第二电极接触。还提供了这种3D通孔电容器的阵列。

40. 发明申请

US20110018575A1 METHOD AND SYSTEM FOR ASSESSING RELIABILITY OF INTEGRATED CIRCUIT 有权
标题翻译：用于评估集成电路可靠性的方法和系统
公开(公告)号：US20110018575A1
公开(公告)日：2011-01-27
申请号：US12508111
申请日：2009-07-23
申请人： Fen Chen , Kai D. Feng , Zhong-Xiang He
发明人： Fen Chen , Kai D. Feng , Zhong-Xiang He
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： G01R31/2621 , G01R31/2855 , G01R31/2894
摘要： The present invention provides a method. The method includes operating a plurality of field-effect-transistors (FETs) under a first operation condition; reversing an operation direction for at least one of the plurality of FETs for a brief period of time; measuring a second operation condition of the one of the plurality of FETs during the brief period of time; computing a difference between the second operation condition and a reference operation condition; and providing a reliability indicator based upon the difference between the second and the reference operation conditions, wherein the plurality of FETs are employed in a single integrated circuit (IC).
摘要翻译：本发明提供一种方法。该方法包括在第一操作条件下操作多个场效应晶体管（FET）; 短时间内反转多个FET中的至少一个的操作方向; 在短时间内测量所述多个FET中的一个的第二操作条件; 计算第二操作条件和参考操作条件之间的差; 以及基于所述第二参考操作条件和所述参考操作条件之间的差异提供可靠性指示器，其中所述多个FET用于单个集成电路（IC）。

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