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31. 发明申请

US20130132063A1 SYSTEMS AND METHODS FOR DEBUGGING JUST-IN-TIME STATIC TRANSLATION IN AN EMULATED SYSTEM 审中-公开
标题翻译：系统和方法，用于调试模拟系统中的一次性静态转换
公开(公告)号：US20130132063A1
公开(公告)日：2013-05-23
申请号：US13299452
申请日：2011-11-18
申请人： Michael J. Rieschl , Mitchell A. Bauman , Feng-Jung Kao , Edward Lusienski , James R. McBreen , James F. Merten , Thomas L. Nowatzki , David W. Schroth , Scott L. Titus , Judge Yohn
发明人： Michael J. Rieschl , Mitchell A. Bauman , Feng-Jung Kao , Edward Lusienski , James R. McBreen , James F. Merten , Thomas L. Nowatzki , David W. Schroth , Scott L. Titus , Judge Yohn
IPC分类号： G06F9/455 , G06F9/45
CPC分类号： G06F9/4552 , G06F11/3624 , G06F11/3688
摘要： Systems and methods for testing and validation of translated memory banks used in an emulated system are disclosed. One method includes translating one or more banks of non-native instructions into one or more banks of native instructions executable in a computing system having a native instruction set architecture. The one or more banks of non-native instructions define one or more tests of execution of a non-native instruction set architecture. The method also includes loading a memory with instructions and data defined according to the non-native instruction set architecture and addressed by the one or more tests, and triggering, by an emulator, execution of the translated one or more banks of native instructions. The method further includes, upon detection of an error during execution of the translated one or more banks of native instructions, identifying an error in execution of the non-native instruction set architecture by the computing system.
摘要翻译：公开了一种用于仿真系统中使用的翻译存储体的测试和验证的系统和方法。一种方法包括将一组或多组非本地指令转换成具有本机指令集架构的计算系统中可执行的一个或多个本地指令库。一个或多个非本机指令组定义了非本地指令集架构的一个或多个执行测试。该方法还包括加载具有根据非本机指令集架构定义并由一个或多个测试寻址的指令和数据的存储器，以及由仿真器触发翻译的一个或多个本地指令库的执行。该方法还包括：在执行翻译的一个或多个本机指令段期间检测到错误时，识别由计算系统执行非本地指令集架构的错误。

32. 发明授权

US06973548B1 Data acceleration mechanism for a multiprocessor shared memory system 有权
标题翻译：多处理器共享内存系统的数据加速机制
公开(公告)号：US06973548B1
公开(公告)日：2005-12-06
申请号：US10600205
申请日：2003-06-20
申请人： Kelvin S. Vartti , Ross M. Weber , Mitchell A. Bauman , Ronald G. Arnold
发明人： Kelvin S. Vartti , Ross M. Weber , Mitchell A. Bauman , Ronald G. Arnold
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0831 , G06F12/0828
摘要： A dual-channel memory system and accompanying coherency mechanism is disclosed. The memory includes both a request and a response channel. The memory provides data to a requester such as an instruction processor via the response channel. If this data is provided for update purposes, other read-only copies of the data must be invalidated. This invalidation may occur after the data is provided for update purposes, and is accomplished by issuing one or more invalidation requests via one of the memory request or the response channel. Memory coherency is maintained by preventing a requester from storing any data back to memory until all invalidation activities that may be directly or indirectly associated with that data have been completed.
摘要翻译：公开了一种双通道存储器系统和附带的一致性机制。存储器包括请求和响应信道。存储器通过响应信道向诸如指令处理器的请求者提供数据。如果提供此数据用于更新目的，数据的其他只读副本必须无效。在为更新目的提供数据之后可能发生这种无效，并且通过经由存储器请求或响应信道之一发出一个或多个无效请求来实现。通过防止请求者将任何数据存储回存储器，直到所有可能与该数据直接或间接相关联的无效活动已经完成来维持内存一致性。

33. 发明授权

US06728835B1 Leaky cache mechanism 失效
标题翻译：泄漏缓存机制
公开(公告)号：US06728835B1
公开(公告)日：2004-04-27
申请号：US09650730
申请日：2000-08-30
申请人： Mitchell A. Bauman , Conrad S. Shimada , Kelvin S. Vartti , William L. Borgerding
发明人： Mitchell A. Bauman , Conrad S. Shimada , Kelvin S. Vartti , William L. Borgerding
IPC分类号： G06F1200
CPC分类号： G06F12/0897 , G06F12/0888 , G06F12/126
摘要： An apparatus for and method of improving the efficiency of a level two cache memory. In response to a level one cache miss, a request is made to the level two cache. A signal sent with the request identifies when the requester does not anticipate a near term subsequent use for the requested data element. If a level two cache hit occurs, the requested data element is marked as least recently used in response to the signal. If a level two cache miss occurs, a request is made to level three storage. When the level three storage request is honored, the requested data element is immediately flushed from the level two cache memory in response to the signal.
摘要翻译：一种用于提高二级高速缓冲存储器的效率的装置和方法。响应于一级缓存未命中，对二级缓存进行请求。与该请求一起发送的信号标识何时请求者不期望对所请求的数据元素的近期使用。如果发生二级缓存命中，则所请求的数据元素被标记为响应于该信号最近最少使用。如果发生二级高速缓存未命中，则要求进行三级存储。当三级存储请求被授予时，响应于该信号立即从二级高速缓冲存储器刷新所请求的数据元素。

34. 发明授权

US06480927B1 High-performance modular memory system with crossbar connections 失效
标题翻译：具有交叉连接的高性能模块化存储系统
公开(公告)号：US06480927B1
公开(公告)日：2002-11-12
申请号：US09001592
申请日：1997-12-31
申请人： Mitchell A. Bauman
发明人： Mitchell A. Bauman
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0813 , G06F13/4022
摘要： A modular, expandable, multi-port main memory system that includes multiple point-to-point switch interconnections and a highly-parallel data path structure that allows multiple memory operations to occur simultaneously. The main memory system includes an expandable number of modular Memory Storage Units, each of which are mapped to a portion of the total address space of the main memory system, and may be accessed simultaneously. Each of the Memory Storage Units includes a predetermined number of memory ports, and an expandable number of memory banks, wherein each of the memory banks may be accessed simultaneously. Each of the memory banks is also modular, and includes an expandable number of memory devices each having a selectable memory capacity. All of the memory devices in the system may be performing different memory read or write operations substantially simultaneously and in parallel. Multiple data paths within each of the Memory Storage Units allow data transfer operations to occur to each of the multiple memory ports in parallel. Simultaneously with the transfer operations occurring to the memory ports, unrelated data transfer operations may occur to multiple ones of the memory devices within all memory banks in parallel. The main memory system further incorporates independent storage devices and control logic to implement a directory-based coherency protocol. Thus the main memory system is adapted to providing the flexibility, bandpass, and memory coherency needed to support a high-speed multiprocessor environment.
摘要翻译：一种模块化，可扩展的多端口主存储系统，包括多个点对点交换机互连以及允许多个存储器操作同时发生的高度并行数据路径结构。主存储器系统包括可扩展数量的模块化存储器单元，每个存储单元被映射到主存储器系统的总地址空间的一部分，并且可以被同时访问。每个存储器存储单元包括预定数量的存储器端口和可扩展数量的存储器组，其中可以同时访问每个存储器组。每个存储体也是模块化的，并且包括每个具有可选存储器容量的可扩展数量的存储器件。系统中的所有存储器件可以基本同时并行地执行不同的存储器读或写操作。每个内存存储单元内的多个数据路径允许数据传输操作并行地发生到多个存储器端口中的每一个。与存储器端口发生的传送操作同时，并行地在所有存储器组中的多个存储器件中可能发生不相关的数据传输操作。主存储系统还包括独立的存储设备和控制逻辑，以实现基于目录的一致性协议。因此，主存储器系统适于提供支持高速多处理器环境所需的灵活性，带通和存储器一致性。

35. 发明授权

US06189078B1 System and method for increasing data transfer throughput for cache purge transactions using multiple data response indicators to maintain processor consistency 有权
标题翻译：用于使用多个数据响应指示器增加缓存清除事务的数据传输吞吐量以维持处理器一致性的系统和方法
公开(公告)号：US06189078B1
公开(公告)日：2001-02-13
申请号：US09218813
申请日：1998-12-22
申请人： Mitchell A. Bauman , Michael L. Haupt
发明人： Mitchell A. Bauman , Michael L. Haupt
IPC分类号： G06F1300
CPC分类号： G06F12/0808
摘要： A system and method for reducing data transfer delays in a transaction processing system is provided. The system includes a plurality of devices each having an associated local memory, and a supervisory memory module having a main storage module for storing data segments and a directory storage for maintaining ownership status of each data segment stored in the main storage module and the local memories. A second device makes a request for a data segment which is stored in a first local memory of a first device. A data transfer request for the requested data segment is transferred from the second device to the supervisory memory module, where the data transfer request includes an identifier requesting permission to modify the requested data segment. The requested data and a data transfer response is delivered to the second device upon receipt of the data transfer request, where the data transfer response provides modification privileges of the requested data segment to the second device. A purge command is issued to the first device to invalidate the copy of the requested data segment in the first local memory. Upon issuance of the purge command to the first device, a purge acknowledge response is delivered to the second device, where the purge acknowledge response provides an indication that the copy of the requested data in the first local memory has been invalidated. The second device is prohibited from releasing any modified data until the purge acknowledge response is received.
摘要翻译：提供了一种用于减少事务处理系统中的数据传输延迟的系统和方法。该系统包括多个具有相关联的本地存储器的设备，以及具有用于存储数据段的主存储模块和用于维持存储在主存储模块和本地存储器中的每个数据段的所有权状态的目录存储器的监控存储器模块。第二设备请求存储在第一设备的第一本地存储器中的数据段。所请求的数据段的数据传输请求从第二设备传送到监控存储器模块，其中数据传输请求包括请求许可修改所请求的数据段的标识符。在接收到数据传输请求时，所请求的数据和数据传输响应被传送到第二设备，其中数据传输响应向所述第二设备提供所请求的数据段的修改特权。向第一设备发出清除命令以使第一本地存储器中所请求的数据段的副本无效。当向第一设备发出清除命令时，清除确认响应被传递到第二设备，其中清除确认响应提供指示第一本地存储器中所请求的数据的副本已经被无效。在接收到清除确认响应之前，禁止第二个设备释放任何修改的数据。

36. 发明授权

US6049845A System and method for providing speculative arbitration for transferring data 失效
标题翻译：提供传输数据的投机仲裁的系统和方法
公开(公告)号：US6049845A
公开(公告)日：2000-04-11
申请号：US964630
申请日：1997-11-05
申请人： Mitchell A. Bauman , Joseph S. Schibinger , Donald R. Kalvestrand , Douglas E. Morrissey
发明人： Mitchell A. Bauman , Joseph S. Schibinger , Donald R. Kalvestrand , Douglas E. Morrissey
IPC分类号： G06F13/18 , G06F12/08 , G06F13/16 , G06F13/362 , G06F15/167 , G06F13/00
CPC分类号： G06F13/1605
摘要： A system and method for optimizing the amount of time it takes for a requestor (device) to receive data from a memory storage unit in a multi-requestor bus environment. The present invention provides a unidirectional response signal, referred to as an early warning signal, sent from a memory storage unit to a device, sometime after that device has executed a fetch request for data, to alert the device that the data is forthcoming. This early warning signal allows the device to arbitrate for the data bus so that when the data arrives, the device will have exclusive ownership of the data bus to accept the data immediately. The present invention comprises a main memory, a cache memory, one or more processor modules, one or more I/O modules, and an early warning bus. The cache memory is connected to the main memory via an interface bus. The processor modules are connected to the cache memory via a processor interface bus. The I/O modules are connected to the main memory via an I/O interface bus. Both the processor modules and the I/O modules include means for requesting a data unit from the main memory. The early warning bus is connected between the main memory, the cache memory, and the I/O module.
摘要翻译：一种用于优化请求者（设备）从多请求者总线环境中的存储器存储单元接收数据所需的时间量的系统和方法。本发明提供了一种从存储器存储单元发送到设备的称为早期警告信号的单向响应信号，该设备在该设备执行了对数据的取出请求之后的某个时刻向该设备通知数据即将到来。该预警信号允许设备对数据总线进行仲裁，以便当数据到达时，设备将具有数据总线的独占所有权以立即接受数据。本发明包括主存储器，高速缓冲存储器，一个或多个处理器模块，一个或多个I / O模块和预警总线。高速缓存通过接口总线连接到主存储器。处理器模块通过处理器接口总线连接到高速缓冲存储器。 I / O模块通过I / O接口总线连接到主存储器。处理器模块和I / O模块都包括用于从主存储器请求数据单元的装置。预警总线连接在主存储器，高速缓冲存储器和I / O模块之间。

37. 发明授权

US4596977A Dual slope analog to digital converter with out-of-range reset 失效
标题翻译：具有超范围复位功能的双斜率模数转换器
公开(公告)号：US4596977A
公开(公告)日：1986-06-24
申请号：US677126
申请日：1984-12-03
申请人： Mitchell A. Bauman , David C. Ullestad
发明人： Mitchell A. Bauman , David C. Ullestad
IPC分类号： H03M1/00
CPC分类号： H03M1/1095 , H03M1/52
摘要： A control method and apparatus for dual slope analog to digital signal conversion is disclosed in which the time required for input signal integration is sensed. A switch connected across the integrator is closed in response to sensing of an integration time which exceeds the integration interval corresponding to a limit of the expected range of input signal values.
摘要翻译：公开了一种用于双斜率模数转换的控制方法和装置，其中检测输入信号积分所需的时间。连接在积分器两端的开关响应于积分时间的检测而被闭合，积分时间超过对应于输入信号值的期望范围的限制的积分间隔。

38. 发明授权

US07634709B2 Familial correction with non-familial double bit error detection 有权
标题翻译：家族性纠正与非家族双位错误检测
公开(公告)号：US07634709B2
公开(公告)日：2009-12-15
申请号：US09972490
申请日：2001-10-05
申请人： Mitchell A. Bauman , Eugene A. Rodi
发明人： Mitchell A. Bauman , Eugene A. Rodi
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/1044
摘要： Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. It uses ×4 bit DRAM devices organized in a code word of 128 data bit words and 16 check bits. These 16 check bits are generated in such a way as to provide a code capable of 4 bit adjacent error correction within a family (i.e., in a ×4 DRAM) and double bit non-adjacent error detection across the entire 128 bit word, with single bit correction across the word as well. Each device can be thought of as a separate family of bits, errors occurring in more than one family are not correctable, but may be detected if only one bit in each of two families is in error. Syndrome generation and regeneration are used together with a specific large code word. Decoding the syndrome and checking it against the regenerated syndrome yield data sufficient for providing the features described.
摘要翻译：与DRAM芯片故障相关的错误校正和错误检测，特别是适配的服务器内存子系统。它使用组织在128个数据位字和16个校验位的代码字中的x4位DRAM器件。这16个校验位的生成方式是提供一个能够在一个系列内进行4位相邻纠错的代码（即，在x4 DRAM中）和跨整个128位字的双位非相邻错误检测的代码，其中单个同时也纠正了这个词。每个设备都可以被认为是一个独立的位系列，发生在多个系列中的错误是不可校正的，但是如果两个系列中的每一个中只有一位是错误的，则可能被检测到。综合征生成和再生与特定的大码字一起使用。对该综合征进行解码并针对再生综合征进行检查，产生足以提供所述特征的数据。

39. 发明授权

US07277825B1 Apparatus and method for analyzing performance of a data processing system 有权
标题翻译：用于分析数据处理系统的性能的装置和方法
公开(公告)号：US07277825B1
公开(公告)日：2007-10-02
申请号：US10423100
申请日：2003-04-25
申请人： Marwan A. Orfali , Mitchell A. Bauman , Myoungran Kim
发明人： Marwan A. Orfali , Mitchell A. Bauman , Myoungran Kim
IPC分类号： G06F11/30
CPC分类号： G06F11/3414 , G06F11/3452
摘要： An improved system and method for completing performance analysis for a target system is disclosed. According to the current invention, different types of configurations files are created, each to describe one or more respective aspects and/or portions of the target system. Each of these file types may include a combination of parameter values and equations that represent the respective portion of the system. After the configuration files are defined, scenarios are created. Each scenario includes a set of configuration files, with some or all of the files being of different file types. The files included within a scenario provide all parameter values and equations needed to calculate performance data for a particular revision of the target system. Next, a performance study is defined to include one or more of the scenarios. Finally, performance data is derived for each of the scenarios in the performance study.
摘要翻译：公开了用于完成目标系统的性能分析的改进的系统和方法。根据本发明，创建不同类型的配置文件，每个配置文件描述目标系统的一个或多个相应方面和/或部分。这些文件类型中的每一个可以包括表示系统的相应部分的参数值和等式的组合。定义配置文件后，将创建方案。每个场景包括一组配置文件，其中一些或全部文件是不同的文件类型。场景中包含的文件提供了计算目标系统特定版本的性能数据所需的所有参数值和方程式。接下来，性能研究被定义为包括一个或多个场景。最后，在性能研究中为每个场景导出性能数据。

40. 发明授权

US07260677B1 Programmable system and method for accessing a shared memory 有权
标题翻译：用于访问共享存储器的可编程系统和方法
公开(公告)号：US07260677B1
公开(公告)日：2007-08-21
申请号：US10620515
申请日：2003-07-16
申请人： Kelvin S. Vartti , Ross M. Weber , Mitchell A. Bauman
发明人： Kelvin S. Vartti , Ross M. Weber , Mitchell A. Bauman
IPC分类号： G06F12/06
CPC分类号： G06F12/0817 , G06F12/084
摘要： A memory control system and method is disclosed. In one embodiment, a first memory is coupled to one or more additional memories. The first memory receives requests for data that are completed by retrieving the data from the first memory and/or the one or more additional memories. The manner in which this data is retrieved is determined by the state of programmable control indicators. In one mode of operation, a reference is made to the first memory to retrieve the data. If it is later determined from tag information stored by the first memory that the one or more additional memories must be accessed to fulfill the request, the necessary additional memory references are initiated. In another mode of operation, references to the one or more additional memories are initiated irrespective of whether these references are required. The operating mode may be selected to optimize system efficiency.
摘要翻译：公开了一种存储器控制系统和方法。在一个实施例中，第一存储器耦合到一个或多个附加存储器。第一存储器通过从第一存储器和/或一个或多个附加存储器检索数据来接收对完成的数据的请求。检索数据的方式由可编程控制指示灯的状态决定。在一种操作模式中，引用第一存储器来检索数据。如果随后由第一存储器存储的标签信息确定必须访问一个或多个附加存储器以满足请求，则启动必要的附加存储器引用。在另一种操作模式中，无论是否需要这些引用，都会启动对一个或多个附加存储器的引用。可以选择操作模式以优化系统效率。

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