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31. 发明授权

US06571332B1 Method and apparatus for combined transaction reordering and buffer management 有权
标题翻译：用于组合事务重新排序和缓冲管理的方法和装置
公开(公告)号：US06571332B1
公开(公告)日：2003-05-27
申请号：US09546979
申请日：2000-04-11
申请人： Paul C. Miranda , Larry D. Hewitt , Stephen C. Ennis
发明人： Paul C. Miranda , Larry D. Hewitt , Stephen C. Ennis
IPC分类号： G06F926
CPC分类号： G06F13/1631
摘要： A method and apparatus for combined transaction reordering and buffer management. The apparatus may include a buffer, a first generator circuit and a second generator circuit. The buffer is configured to store memory transaction responses received from a memory controller in a plurality of addressable locations. The first generator circuit is configured to generate a first memory transaction request encoded with a first tag corresponding to an address in the buffer in response to receiving a first memory request. The second generator circuit is configured to generate a second tag using the size of said first memory request added to the first tag. The first generator circuit may be further configured to generate a second memory transaction request encoded with the second tag corresponding to a second address in the buffer in response to receiving a second memory request successive to the first memory request. The second generator circuit may be further configured to generate a third tag using the size of the second memory request added to said second tag.
摘要翻译：一种用于组合事务重新排序和缓冲管理的方法和装置。该装置可以包括缓冲器，第一发生器电路和第二发生器电路。缓冲器被配置为存储在多个可寻址位置中从存储器控制器接收的存储器事务响应。第一发生器电路被配置为响应于接收到第一存储器请求而产生用与缓冲器中的地址相对应的第一标签编码的第一存储器事务请求。第二发生器电路被配置为使用添加到第一标签的所述第一存储器请求的大小来生成第二标签。第一生成器电路可以被配置为响应于接收到与第一存储器请求连续的第二存储器请求，来生成与缓冲器中的第二地址对应的第二标签编码的第二存储器事务请求。第二发生器电路还可以被配置为使用添加到所述第二标签的第二存储器请求的大小来生成第三标签。

32. 发明授权

US06532019B1 Input/output integrated circuit hub incorporating a RAMDAC 有权
标题翻译：包含RAMDAC的输入/输出集成电路集线器
公开(公告)号：US06532019B1
公开(公告)日：2003-03-11
申请号：US09502068
申请日：2000-02-10
申请人： Dale E. Gulick , Larry D. Hewitt
发明人： Dale E. Gulick , Larry D. Hewitt
IPC分类号： G06F1576
CPC分类号： G06F13/4213 , Y02D10/14 , Y02D10/151
摘要： A computer system includes a first integrated circuit that has a central processing unit (CPU) and a graphics controller. An I/O hub, which is coupled to a plurality of input/output buses, includes a RAMDAC. An interconnect bus couples the first integrated circuit and the I/O hub and carries both graphics data to or from a frame buffer and also carries asynchronous system data between the processor and the input/output integrated circuit. The frame buffer may be located in the I/O hub to reduce graphics traffic over the interconnect bus.
摘要翻译：计算机系统包括具有中央处理单元（CPU）和图形控制器的第一集成电路。耦合到多个输入/输出总线的I / O集线器包括RAMDAC。互连总线耦合第一集成电路和I / O集线器，并将图形数据传送到帧缓冲器或从帧缓冲器传送，并且还在处理器和输入/输出集成电路之间传送异步系统数据。帧缓冲器可以位于I / O集线器中，以减少互连总线上的图形流量。

33. 发明授权

US5809466A Audio processing chip with external serial port 失效
标题翻译：音频处理芯片带外部串口
公开(公告)号：US5809466A
公开(公告)日：1998-09-15
申请号：US753719
申请日：1996-11-27
申请人： Larry D. Hewitt , Glen W. Brown , Dale E. Gulick , Michael Hogan , David Norris , Martin P. Soques , David N. Suggs
发明人： Larry D. Hewitt , Glen W. Brown , Dale E. Gulick , Michael Hogan , David Norris , Martin P. Soques , David N. Suggs
IPC分类号： G06F7/02 , H03K23/68 , G10L5/00
CPC分类号： H03K23/68 , G06F7/026
摘要： This invention is for a single monolithic audio processing integrated circuit which includes a synthesizer module, a CODEC module and an external serial data port in the CODEC module for bi-directional serial data communication between the CODEC module and an external serial data device, such as a digital signal processor. A serial data path between the synthesizer module and the CODEC module is also included.
摘要翻译：本发明是用于单个单片音频处理集成电路，其包括CODEC模块中的合成器模块，CODEC模块和外部串行数据端口，用于CODEC模块和外部串行数据设备之间的双向串行数据通信，例如数字信号处理器。还包括合成器模块和CODEC模块之间的串行数据路径。

34. 发明授权

US5675808A Power control of circuit modules within an integrated circuit 失效
标题翻译：集成电路内电路模块的功率控制
公开(公告)号：US5675808A
公开(公告)日：1997-10-07
申请号：US333537
申请日：1994-11-02
申请人： Dele E. Gulick , Larry D. Hewitt , Michael Hogan , David Norris
发明人： Dele E. Gulick , Larry D. Hewitt , Michael Hogan , David Norris
IPC分类号： G06F7/02 , H03K23/68 , G06F1/32
CPC分类号： H03K23/68 , G06F7/026
摘要： A power control and memory refresh rate management circuit is described. The power control circuit provides circuitry for selectively disabling or enabling modular logic circuit blocks within a VLSI integrated circuit under program control from an external processor, or for suspended circuit operation in general. In low-power modes external memory refresh signal generation circuits are provided with a low-frequency oscillator signal to conserve power.
摘要翻译：描述了功率控制和存储器刷新率管理电路。功率控制电路提供电路，用于在来自外部处理器的程序控制下选择性地禁用或启用VLSI集成电路内的模块化逻辑电路块，或者通常用于暂停电路操作。在低功率模式下，外部存储器刷新信号发生电路具有低频振荡器信号以节省功率。

35. 发明授权

US5668338A Wavetable audio synthesizer with low frequency oscillators for tremolo and vibrato effects 失效
标题翻译：具有低频振荡器的波音音频合成器，用于颤音和颤音效果
公开(公告)号：US5668338A
公开(公告)日：1997-09-16
申请号：US333564
申请日：1994-11-02
申请人： Larry D. Hewitt , David N. Suggs , David Norris
发明人： Larry D. Hewitt , David N. Suggs , David Norris
IPC分类号： G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68 , G10H1/02
CPC分类号： H03K23/68 , G06F3/162 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/611
摘要： A digital wavetable audio synthesizer with an LFO generator is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. The LFO generator assigns two triangular-wave LFOs to each of the 32 possible voices. One LFO is dedicated to vibrato (frequency modulation) effects and the other to tremolo (amplitude modulation) effects. It is possible to ramp the depth of each LFO into and out of a programmable maximum. The parameters for each LFO are stored in local memory. When creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations can be added to the read address to create chorus and flange effects.
摘要翻译：描述了具有LFO发生器的数字波表音频合成器。合成器可以生成多达32个高质量的音频数字信号或声音，包括基于延迟的效果。合成器包括地址发生器，其具有寻址波形数据的几种模式。地址发生器的寻址速率控制合成器输出信号的间距。合成器音量发生器具有多种控制音量的模式，为数据添加了包络，右偏移，左偏移和效果音量。合成器LFO发生器可以添加LFO变化：（i）波形数据寻址速率，用于产生颤音效果; 和（ii）声音的音量，用于产生颤音效果。 LFO发生器为32个可能的声音中的每一个分配两个三角波LFO。一个LFO专用于颤音（调频）效果，另一个用于颤音（振幅调制）效果。可以将每个LFO的深度倾斜到可编程最大值之外。每个LFO的参数存储在本地存储器中。当创建基于延迟的效果时，数据存储在几个效果累加器之一中。然后将此数据写入波表。该数据的波形写入和读取地址之间的差异提供了回声和混响效应的延迟。 LFO变体可以添加到读取地址以创建合唱和法兰效果。

36. 发明授权

US07986727B2 In-band method to configure equalization levels 有权
标题翻译：配置均衡电平的带内方式
公开(公告)号：US07986727B2
公开(公告)日：2011-07-26
申请号：US11614529
申请日：2006-12-21
申请人： Gerald R. Talbot , Larry D. Hewitt , Paul C. Miranda , Rohit Kumar , Emerson S. Fang
发明人： Gerald R. Talbot , Larry D. Hewitt , Paul C. Miranda , Rohit Kumar , Emerson S. Fang
IPC分类号： H04B1/38
CPC分类号： H04L25/03878 , H04L7/0008 , H04L7/0091 , H04L2025/03592
摘要： An in-band configuration technique configures a data communications link for high-speed data communications between at least a first and second integrated circuit using in-band communications between the first and second integrated circuits. The technique configures at least one equalizer of the data communications link with predetermined equalizer settings selected from a plurality of predetermined equalizer settings based on a selected rate of data communications for the link.
摘要翻译：带内配置技术使用第一和第二集成电路之间的带内通信来配置用于在至少第一和第二集成电路之间的高速数据通信的数据通信链路。该技术基于针对该链路的所选择的数据通信速率，从至少一个预定均衡器设置中选择的预定均衡器设置配置数据通信链路的至少一个均衡器。

37. 发明授权

US07455450B2 Method and apparatus for temperature sensing in integrated circuits 失效
标题翻译：集成电路中温度检测的方法和装置
公开(公告)号：US07455450B2
公开(公告)日：2008-11-25
申请号：US11246855
申请日：2005-10-07
申请人： Huining Liu , Larry D. Hewitt
发明人： Huining Liu , Larry D. Hewitt
IPC分类号： G01K3/00
CPC分类号： G01K7/203
摘要： A method and apparatus for temperature sensing in an IC. The IC includes a plurality of remote temperature sensors each coupled to a control logic unit. The plurality of remote temperature sensors may be distributed throughout the integrated circuit. The integrated circuit includes a reference unit coupled to provide a reference temperature to the control logic unit and a reference sensor coupled to provide a signal having a reference frequency to the control logic unit. The reference unit and the reference sensor are located near each other. The control logic unit is configured to correlate the reference frequency received from the reference sensor with the reference temperature received from the reference unit. The control logic unit is further configured to determine the temperature of each of the remote temperature sensors based on this correlation, and also configured to determine the maximum temperature of all of the temperature sensors.
摘要翻译：一种用于IC中温度感测的方法和装置。 IC包括多个远程温度传感器，每个远程温度传感器都耦合到控制逻辑单元。多个远程温度传感器可以分布在整个集成电路中。该集成电路包括一个参考单元，该参考单元被耦合以向控制逻辑单元提供参考温度，以及一个参考传感器，该参考传感器被耦合以向控制逻辑单元提供具有参考频率的信号。参考单元和参考传感器彼此靠近。控制逻辑单元被配置为将从参考传感器接收的参考频率与从参考单元接收的参考温度相关联。控制逻辑单元还被配置为基于该相关性来确定每个远程温度传感器的温度，并且还被配置为确定所有温度传感器的最高温度。

38. 发明授权

US07451337B1 Guaranteed edge synchronization for multiple clocks 失效
标题翻译：保证多个时钟的边沿同步
公开(公告)号：US07451337B1
公开(公告)日：2008-11-11
申请号：US10266152
申请日：2002-10-07
申请人： Larry D. Hewitt
发明人： Larry D. Hewitt
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： G06F1/12 , G06F1/10
摘要： A method and apparatus for guaranteeing clock edge synchronization is disclosed. In one embodiment, a system for synchronizing clock signals includes a clock unit and a synchronization unit. Both the clock unit and the synchronization unit may be configured to receive a reference clock signal. The clock unit may be configured to drive a plurality of domain clock signals to various clock domains. The synchronization unit may be configured to assert a synchronization pulse once every N reference clock cycles. Clock edges of the domain clock signals may be aligned with each other responsive to asserting the synchronization pulse.
摘要翻译：公开了一种用于保证时钟沿同步的方法和装置。在一个实施例中，用于同步时钟信号的系统包括时钟单元和同步单元。时钟单元和同步单元都可以被配置为接收参考时钟信号。时钟单元可以被配置为将多个域时钟信号驱动到各种时钟域。同步单元可以被配置为每N个参考时钟周期一次断言同步脉冲。响应于断言同步脉冲，域时钟信号的时钟边缘可以彼此对准。

39. 发明授权

US07174467B1 Message based power management in a multi-processor system 有权
标题翻译：多处理器系统中基于消息的电源管理
公开(公告)号：US07174467B1
公开(公告)日：2007-02-06
申请号：US10185171
申请日：2002-06-28
申请人： Frank P. Helms , Dale E. Gulick , Larry D. Hewitt , William A. Hughes , Paul C. Miranda , Derrick R. Meyer , Scott E. Swanstrom , Scott A. White
发明人： Frank P. Helms , Dale E. Gulick , Larry D. Hewitt , William A. Hughes , Paul C. Miranda , Derrick R. Meyer , Scott E. Swanstrom , Scott A. White
IPC分类号： G06F1/26 , G06F1/28 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3296 , G06F9/30083 , Y02D10/126 , Y02D10/172
摘要： A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the processors of the multi-processor system. The power management message includes a power management field encoding a power management state for processors of the multi-processor system. The processor that received the power management message over the input/output communication link sends a power management message to other processors in the multi-processor system over one or more inter-processor communication links encoding the power management state.
摘要翻译：利用基于消息的电源管理方法为多处理器系统提供电源管理。在多处理器系统的一个处理器上通过输入/输出通信链路接收功率管理消息，该输入/输出通信链路为多处理器系统的处理器提供输入/输出接入。电源管理消息包括对多处理器系统的处理器编码电源管理状态的电源管理字段。通过输入/输出通信链路接收电力管理消息的处理器通过编码电源管理状态的一个或多个处理器间通信链路向多处理器系统中的其他处理器发送电源管理消息。

40. 发明授权

US07051218B1 Message based power management 有权
标题翻译：基于消息的电源管理
公开(公告)号：US07051218B1
公开(公告)日：2006-05-23
申请号：US10185195
申请日：2002-06-28
申请人： Dale E. Gulick , Frank P. Helms , Larry D. Hewitt , William A. Hughes , Paul C. Miranda , Derrick R. Meyer , Scott E. Swanstrom , Scott A. White
发明人： Dale E. Gulick , Frank P. Helms , Larry D. Hewitt , William A. Hughes , Paul C. Miranda , Derrick R. Meyer , Scott E. Swanstrom , Scott A. White
IPC分类号： G06F1/30 , G06F3/00 , G06F13/36
CPC分类号： G06F1/3209 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F1/3296 , G06F9/30083 , Y02D10/126 , Y02D10/151 , Y02D10/172
摘要： A message based power management system converts legacy signals used in power management, and other signals used to differentiate between power states, to messages sent over a communication link. A system message sent on a communication link includes a field encoding the level of power management for the device receiving the system message. Further, one or more additional signals, separate from the communication link, may be used to indicate when to take action after the power management message has been received.
摘要翻译：基于消息的电力管理系统将用于电力管理的传统信号和用于区分电力状态的其他信号转换成通过通信链路发送的消息。在通信链路上发送的系统消息包括对接收系统消息的设备的电源管理级进行编码的字段。此外，与通信链路分离的一个或多个附加信号可以用于指示何时在接收到电力管理消息之后采取行动。

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