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31. 发明授权

US5721658A Input/output electrostatic discharge protection for devices with multiple individual power groups 失效
公开(公告)号：US5721658A
公开(公告)日：1998-02-24
申请号：US625333
申请日：1996-04-01
申请人： Manny K. F. Ma , Jeffrey P. Wright
发明人： Manny K. F. Ma , Jeffrey P. Wright
IPC分类号： H02H9/04 , H02H3/22
CPC分类号： H02H9/046
摘要： An electrostatic discharge protection system for an integrated circuit device, such as a solid state memory device or any other integrated circuit device having a plurality of individual power groups, includes a loop of an electrically conductive material that is disposed on the device defining a electrostatic discharge path portion, a plurality of first punch-through devices which connect the input/output pins of different power groups of the integrated circuit device to the power sources of the associated power group, and a plurality of second punch-through devices which connect all of the input/output pins of the integrated circuit device to the electrostatic discharge path portion, thereby providing a discharge path that is common to all of the power groups of the integrated circuit device.

32. 发明授权

US5679593A Method of fabricating a high resistance integrated circuit resistor 失效
标题翻译：制造高阻集成电路电阻的方法
公开(公告)号：US5679593A
公开(公告)日：1997-10-21
申请号：US595232
申请日：1996-02-01
申请人： James E. Miller, Jr. , Manny K. F. Ma
发明人： James E. Miller, Jr. , Manny K. F. Ma
IPC分类号： H01L21/329 , H01L21/8238 , H01L27/06 , H01L29/8605 , H01L21/265
CPC分类号： H01L29/66166 , H01L21/8238 , H01L27/0629 , H01L29/8605 , Y10S148/136
摘要： The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.
摘要翻译：本发明教导了制造使用标准CMOS工艺步骤的高电阻集成电路扩散电阻器。在源极/漏极扩散区的离子注入期间通过适当的掩蔽，在NMOS源极/漏极注入期间产生的扩散电阻器可能在PMOS源极/漏极注入期间被反掺杂，反之亦然。通过适当选择电阻器掺杂剂和反掺杂剂的相对浓度以及扩散深度的选择，可以形成结二极管，其通过限制电流流动而产生夹持电阻。还可以选择相对掺杂剂浓度以在扩散电阻器内产生光有效掺杂的区域，而不是产生结二极管。

33. 发明授权

US5663919A Memory device with regulated power supply control 失效
标题翻译：具有稳压电源控制的存储器件
公开(公告)号：US5663919A
公开(公告)日：1997-09-02
申请号：US608444
申请日：1996-02-28
申请人： Brian M. Shirley , Manny K. F. Ma , Gordon Roberts
发明人： Brian M. Shirley , Manny K. F. Ma , Gordon Roberts
IPC分类号： G11C5/14 , G11C7/00 , G11C11/4074
CPC分类号： G11C5/14 , G11C11/4074 , G11C5/147
摘要： A memory device is described which includes a voltage regulator having a low power standby mode. A voltage regulator control circuit is described which places the voltage regulator in a high current mode when the outputs of the memory device are active. The regulator control circuit is operated in response to a combination of RAS*, CAS* and OE* signals.
摘要翻译：描述了一种存储器件，其包括具有低功率待机模式的电压调节器。描述了一种电压调节器控制电路，其在存储器件的输出有效时将电压调节器置于高电流模式。调节器控制电路响应于RAS *，CAS *和OE *信号的组合而工作。

34. 发明授权

US07903379B2 Cascode I/O driver with improved ESD operation 有权
标题翻译：串行I / O驱动器，具有改进的ESD操作
公开(公告)号：US07903379B2
公开(公告)日：2011-03-08
申请号：US11831420
申请日：2007-07-31
申请人： Michael D. Chaine , Manny K. F. Ma
发明人： Michael D. Chaine , Manny K. F. Ma
IPC分类号： H02H9/00
CPC分类号： H01L29/7831 , H01L27/0266 , H01L29/0649 , H01L29/0692 , H01L29/41725
摘要： A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.
摘要翻译：描述了包括形成在两个晶体管之间的共享区域中的屏障的级联I / O驱动器。屏障区域允许I / O驱动程序设计为主要满足I / O要求。因此，实现了改进的操作速度。描述了包括与ESD装置并联的I / O驱动器的系统。在一个实施例中，在ESD开始导通之后，I / O驱动器可以辅助静电装置放电静电。

35. 发明授权

US06579746B2 Method and apparatus for coupling a semiconductor die to die terminals 有权
公开(公告)号：US06579746B2
公开(公告)日：2003-06-17
申请号：US09932080
申请日：2001-08-17
申请人： Aaron Schoenfeld , Manny K. F. Ma , Larry D. Kinsman , J. Mike Brooks , Timothy J. Allen
发明人： Aaron Schoenfeld , Manny K. F. Ma , Larry D. Kinsman , J. Mike Brooks , Timothy J. Allen
IPC分类号： H01L2144
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/49838 , H01L23/642 , H01L23/645 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48599 , H01L2224/48699 , H01L2224/49171 , H01L2224/49433 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2924/00012
摘要： A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals. The first and second conductive members may each have an intermediate portion between the first and second end portions thereof that is narrower than the second end portions thereof, and the conductive members may be staggered by axially offsetting the second end portion of the second conductive member from the second end portion of the first conductive member.

36. 发明授权

US06391755B2 Method of making EEPROM transistor for a DRAM 失效
标题翻译：制造用于DRAM的EEPROM晶体管的方法
公开(公告)号：US06391755B2
公开(公告)日：2002-05-21
申请号：US09361471
申请日：1999-07-27
申请人： Manny K. F. Ma , Yauh-Ching Liu
发明人： Manny K. F. Ma , Yauh-Ching Liu
IPC分类号： H01L213205
CPC分类号： H01L27/10852 , H01L27/105 , H01L27/1052
摘要： A floating gate transistor is formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions. Conventional DRAM process steps are used to form cell storage capacitors in all the buried contact openings, including buried contact openings on EEPROM transistor gates. An EEPROM transistor gate and its associated cell storage capacitor bottom plate together forms a floating gate completely surrounded by insulating material. The top cell storage capacitor plate on an EEPROM transistor is used as a control gate to apply programming voltages to the EEPROM transistor. Reading, writing, and erasing the EEPROM element are analogous to conventional floating-gate tunneling oxide (FLOTOX) EEPROM devices. In this way, existing DRAM process steps are used to implement an EEPROM floating gate transistor nonvolatile memory element.
摘要翻译：通过在EEPROM晶体管栅极和DRAM存取晶体管源极/漏极扩散两者上同时产生掩埋接触开口形成浮栅晶体管。常规DRAM工艺步骤用于在所有掩埋的接触开口中形成电池存储电容器，包括EEPROM晶体管栅极上的埋入式接触开口。 EEPROM晶体管栅极及其相关的电池存储电容器底板一起形成完全被绝缘材料包围的浮动栅极。 EEPROM晶体管上的顶部单元存储电容器板用作控制栅极，以将编程电压施加到EEPROM晶体管。读取，写入和擦除EEPROM元件类似于常规浮栅隧道氧化物（FLOTOX）EEPROM器件。以这种方式，现有的DRAM处理步骤用于实现EEPROM浮栅晶体管非易失性存储元件。

37. 发明授权

US06252293B1 Laser antifuse using gate capacitor 失效
标题翻译：激光反熔丝采用栅极电容
公开(公告)号：US06252293B1
公开(公告)日：2001-06-26
申请号：US09109605
申请日：1998-07-02
申请人： Mirmajid Seyyedy , Manny K. F. Ma
发明人： Mirmajid Seyyedy , Manny K. F. Ma
IPC分类号： H01L2900
CPC分类号： G11C17/16 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit laser antifuse is described which has two physical states. In the first physical state the laser antifuse has to conductive plates electrically separated by a layer of dielectric material. In the second physical state the two conductive plates are electrically connected through the dielectric in response to an external radiation source, such as a laser.
摘要翻译：描述了具有两种物理状态的集成电路激光反熔丝。在第一物理状态下，激光反熔丝必须具有由介电材料层电隔离的导电板。在第二物理状态下，响应于诸如激光器的外部辐射源，两个导电板通过电介质电连接。

38. 发明授权

US6137664A Well resistor for ESD protection of CMOS circuits 有权
标题翻译：用于CMOS电路ESD保护的良好电阻
公开(公告)号：US6137664A
公开(公告)日：2000-10-24
申请号：US231137
申请日：1999-01-15
申请人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
发明人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
IPC分类号： H01L21/8242 , H01L27/02 , H01L27/108 , H02H9/00
CPC分类号： H01L27/0288 , H01L27/0266
摘要： A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them between supply and ground busses respectively. During an ESD event, the well resistors serve to both limit the current flow through the transistors, and reduce the voltage drop across them.
摘要翻译：公开了一种用于提供静电放电（ESD）保护的电路。该电路包括一对具有减小的电阻源和漏极的CMOS场效应上拉和下拉晶体管，其中分别在供电和接地总线之间形成在其外部的阱电阻器。在ESD事件期间，阱电阻用于限制通过晶体管的电流，并且减小它们之间的电压降。

39. 发明授权

US6111806A Memory device with regulated power supply control 有权
标题翻译：具有稳压电源控制的存储器件
公开(公告)号：US6111806A
公开(公告)日：2000-08-29
申请号：US317907
申请日：1999-05-24
申请人： Brian M. Shirley , Manny K. F. Ma , Gordon Roberts
发明人： Brian M. Shirley , Manny K. F. Ma , Gordon Roberts
IPC分类号： G11C5/14 , G11C7/00 , G11C11/4074
CPC分类号： G11C5/14 , G11C11/4074 , G11C5/147
摘要： A memory device is described which includes a voltage regulator having a low power standby mode. A voltage regulator control circuit is described which places the voltage regulator in a high current mode when the outputs of the memory device are active. The regulator control circuit is operated in response to a combination of RAS*, CAS* and OE* signals.
摘要翻译：描述了一种存储器件，其包括具有低功率待机模式的电压调节器。描述了一种电压调节器控制电路，其在存储器件的输出有效时将电压调节器置于高电流模式。调节器控制电路响应于RAS *，CAS *和OE *信号的组合而工作。

40. 发明授权

US06060896A Super-voltage circuit with a fast reset 失效
标题翻译：具有快速复位的超压电路
公开(公告)号：US06060896A
公开(公告)日：2000-05-09
申请号：US977339
申请日：1997-11-24
申请人： Manny K. F. Ma , Joseph C. Sher
发明人： Manny K. F. Ma , Joseph C. Sher
IPC分类号： G01R31/317 , G01R31/28
CPC分类号： G01R31/31701
摘要： A super-voltage circuit with a fast reset capability is formed in an integrated circuit for generating a test mode logic state for testing other circuits in the same integrated circuit. The super-voltage circuit includes a sensing circuit, a reset circuit, and an output circuit connected to both the sensing circuit and the reset circuit. When the input voltage receives a super-voltage which is higher than either the logic high or low voltages, the sensing circuit generates at its output a high voltage. The reset circuit also receiving the same input voltage as the sensing circuit generates at its output a logic low state when the input voltage is at the super-voltage or logic high voltage. When the sensing circuit is generating the high voltage and the reset circuit is generating the logic low state the output circuit generates at its output a logic low voltage. The logic low voltage signifies that the integrated circuit is now in the super-voltage test mode. To terminate the test mode, the super-voltage is removed from the input of the sensing circuit. As the input voltage falls to 0 volts, the reset circuit generates a logic high voltage. In response to the logic high voltage, the output circuit quickly resets its output to a logic high state signifying that the integrated circuit is now in a normal operational mode.
摘要翻译：在集成电路中形成具有快速复位能力的超压电路，用于产生用于测试同一集成电路中的其它电路的测试模式逻辑状态。超级电压电路包括感测电路，复位电路和连接到感测电路和复位电路的输出电路。当输入电压接收到高于逻辑高电平或低电压的超级电压时，感测电路在其输出端产生高电压。当输入电压处于超电压或逻辑高电压时，复位电路还接收与感测电路在其输出端产生逻辑低电平的相同的输入电压。当感测电路产生高电压并且复位电路产生逻辑低电平状态时，输出电路在其输出端产生逻辑低电压。逻辑低电压表示集成电路现在处于超电压测试模式。为了终止测试模式，从感测电路的输入端去除超电压。当输入电压降至0伏时，复位电路产生逻辑高电压。响应于逻辑高电压，输出电路将其输出快速复位到逻辑高电平状态，表示集成电路现在处于正常工作模式。

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