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31. 发明授权

US07447086B2 Selective program voltage ramp rates in non-volatile memory 有权
标题翻译：非易失性存储器中的选择性编程电压斜坡率
公开(公告)号：US07447086B2
公开(公告)日：2008-11-04
申请号：US11866261
申请日：2007-10-02
申请人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Jan Hemink , Ken Oowada , Jian Chen , Geoffrey S Gongwer
发明人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Jan Hemink , Ken Oowada , Jian Chen , Geoffrey S Gongwer
IPC分类号： G11C7/00
CPC分类号： G11C16/3418
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。基于正在编程的字线选择程序禁止方案。已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。可以基于系统的温度来选择程序禁止方案。

32. 发明申请

US20070159888A1 FLASH MEMORY DEVICES WITH TRIMMED ANALOG VOLTAGES 有权
标题翻译：具有TRIMMED模拟电压的闪存存储器件
公开(公告)号：US20070159888A1
公开(公告)日：2007-07-12
申请号：US11332567
申请日：2006-01-12
申请人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
发明人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C7/16 , G11C11/5628 , G11C16/04 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C27/005 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/50004 , G11C2029/5004 , G11C2211/5621 , G11C2211/5634
摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.
摘要翻译：公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值它提供了选择用于正常操作的最接近的结果。这些DAC取决于我也被修剪的参考源的值。

33. 发明申请

US20080019180A1 Selective Program Voltage Ramp Rates in Non-Volatile Memory 有权
标题翻译：非易失性存储器中的选择性编程电压斜坡率
公开(公告)号：US20080019180A1
公开(公告)日：2008-01-24
申请号：US11866261
申请日：2007-10-02
申请人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Hemink , Ken Oowada , Jian Chen , Geoffrey Gongwer
发明人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Hemink , Ken Oowada , Jian Chen , Geoffrey Gongwer
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/3418
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。基于正在编程的字线选择程序禁止方案。已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。可以基于系统的温度来选择程序禁止方案。

34. 发明授权

US07295478B2 Selective application of program inhibit schemes in non-volatile memory 有权
标题翻译：在非易失性存储器中选择性地应用程序抑制方案
公开(公告)号：US07295478B2
公开(公告)日：2007-11-13
申请号：US11127743
申请日：2005-05-12
申请人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Jan Hemink , Ken Oowada , Jian Chen , Geoffrey S. Gongwer
发明人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Jan Hemink , Ken Oowada , Jian Chen , Geoffrey S. Gongwer
IPC分类号： G11C7/00
CPC分类号： G11C16/3418
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。基于正在编程的字线选择程序禁止方案。已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。可以基于系统的温度来选择程序禁止方案。

35. 发明申请

US20060279990A1 Selective application of program inhibit schemes in non-volatile memory 有权
标题翻译：在非易失性存储器中选择性地应用程序抑制方案
公开(公告)号：US20060279990A1
公开(公告)日：2006-12-14
申请号：US11127743
申请日：2005-05-12
申请人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Hemink , Ken Oowada , Jian Chen , Geoffrey Gongwer
发明人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Hemink , Ken Oowada , Jian Chen , Geoffrey Gongwer
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。基于正在编程的字线选择程序禁止方案。已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。可以基于系统的温度来选择程序禁止方案。

36. 发明授权

US08737125B2 Aggregating data latches for program level determination 有权
标题翻译：汇总数据锁存器进行程序级确定
公开(公告)号：US08737125B2
公开(公告)日：2014-05-27
申请号：US13569008
申请日：2012-08-07
申请人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
发明人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/34
摘要： In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results.
摘要翻译：在存储随机化数据的非易失性存储器阵列中，可以从单个读取步骤的聚合结果确定程序级 - 存储在存储器单元群中的每个存储单元的状态数。用于聚合读取步骤的二进制结果的电路包括具有连接到保持二进制结果的数据锁存器的控制栅极的并行晶体管，使得通过组合晶体管的电流依赖于二进制结果。

37. 发明授权

US08453726B2 Corrugated settling cup and a multi-cup uniform flux gas anchor 有权
标题翻译：波纹沉降杯和多杯均匀通量气锚
公开(公告)号：US08453726B2
公开(公告)日：2013-06-04
申请号：US12673064
申请日：2008-08-22
申请人： Demin Wang , Yan Wang , Jun Wan , Shumin Zhang , Rongjie Zhu , Li Li
发明人： Demin Wang , Yan Wang , Jun Wan , Shumin Zhang , Rongjie Zhu , Li Li
IPC分类号： E21B43/38
CPC分类号： E21B43/38 , E21B43/127 , F04B47/02
摘要： A corrugated settling cup (5) is provided, wherein the cup has a cup body, an opening and a location step (52) are provided at the bottom (55) of the cup body, several location holes (53) are formed at the top of the location step (52), location projections (54) corresponding to the location holes (53) are formed at the bottom (55) of the corrugated settling cup (5), wherein the external profile of the corrugated settling cup body rises along the axial direction in a corrugated shape. A multi-cup uniform flux gas anchor is provided, wherein the gas anchor includes a central pipe (7), several corrugated settling cups (5), several settling cups protection bodies (6) and a well-flushing valve (9), wherein the external profile of the corrugated settling cup body rises along the axial direction in a corrugated shape.
摘要翻译：提供了一种波纹沉降杯（5），其中杯体具有杯体，在杯体的底部（55）设有开口和位置台阶（52），多个位置孔（53）形成在在波纹沉降杯（5）的底部（55）形成位置台阶（52）的顶部，对应于定位孔（53）的定位突起（54），其中波纹沉降杯体的外部轮廓上升沿轴向以波纹形状。提供了一种多杯均匀的通量气体锚定器，其中气锚包括中心管（7），多个波纹沉降杯（5），多个沉降杯保护体（6）和井冲洗阀（9），其中波纹沉降杯体的外部轮廓沿轴向方向以波纹形状上升。

38. 发明授权

US08379454B2 Detection of broken word-lines in memory arrays 有权
标题翻译：检测存储器阵列中断字符
公开(公告)号：US08379454B2
公开(公告)日：2013-02-19
申请号：US13101765
申请日：2011-05-05
申请人： Mrinal Kochar , Jianmin Huang , Jun Wan
发明人： Mrinal Kochar , Jianmin Huang , Jun Wan
IPC分类号： G11C16/04
CPC分类号： G11C29/52 , G11C16/3418 , G11C16/3459 , G11C29/025
摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. An “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. The number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.
摘要翻译：提供技术和相应的电路用于检测存储器阵列中的断字。比较不同字线的程序循环计数的字间对比比较，以确定字线是否有缺陷。将沿着字线WLn的单元所需的编程脉冲的数量与前一字线（例如WLn或WL（n-1））所需的数字进行比较，以查看其是否超过该较早的值一个阈值值。如果字线需要过多的脉冲数，相对于较早的字线，要完成编程，则将其视为有缺陷的。

39. 发明授权

US08368137B2 Dual bit line metal layers for non-volatile memory 有权
标题翻译：用于非易失性存储器的双位线金属层
公开(公告)号：US08368137B2
公开(公告)日：2013-02-05
申请号：US11768468
申请日：2007-06-26
申请人： Nima Mokhlesi , Jun Wan
发明人： Nima Mokhlesi , Jun Wan
IPC分类号： H01L29/788
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1006 , G11C7/18 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4ƒpitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.
摘要翻译：公开了用于在非易失性存储系统中减少位线到位线电容的结构和技术。位线在两个分离的金属层中的每一个中以4fpitch形成，并且布置成在每个层之间交替。在替代实施例中，在每个金属层上的每个位线之间形成屏蔽。

40. 发明申请

US20120281479A1 Detection of Broken Word-Lines in Memory Arrays 有权
标题翻译：在内存数组中检测破碎的字线
公开(公告)号：US20120281479A1
公开(公告)日：2012-11-08
申请号：US13101765
申请日：2011-05-05
申请人： Mrinal Kochar , Jianmin Huang , Jun Wan
发明人： Mrinal Kochar , Jianmin Huang , Jun Wan
IPC分类号： G11C16/10
CPC分类号： G11C29/52 , G11C16/3418 , G11C16/3459 , G11C29/025
摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. One example considers an “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. For example, the number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.
摘要翻译：提供技术和相应的电路用于检测存储器阵列中的断字。一个例子考虑比较不同字线的程序循环计数以便确定字线是否有缺陷的字间对比比较。例如，将沿着字线WLn的单元所需的编程脉冲的数量与先前的字线（例如WLn或WL（n-1））所需的数字进行比较，以查看其是否超过该较早的值通过阈值。如果字线需要过多的脉冲数，相对于较早的字线，要完成编程，则将其视为有缺陷的。

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