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1. 发明授权

US07447086B2 Selective program voltage ramp rates in non-volatile memory 有权
标题翻译：非易失性存储器中的选择性编程电压斜坡率
公开(公告)号：US07447086B2
公开(公告)日：2008-11-04
申请号：US11866261
申请日：2007-10-02
申请人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Jan Hemink , Ken Oowada , Jian Chen , Geoffrey S Gongwer
发明人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Jan Hemink , Ken Oowada , Jian Chen , Geoffrey S Gongwer
IPC分类号： G11C7/00
CPC分类号： G11C16/3418
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。基于正在编程的字线选择程序禁止方案。已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。可以基于系统的温度来选择程序禁止方案。

2. 发明授权

US07295478B2 Selective application of program inhibit schemes in non-volatile memory 有权
标题翻译：在非易失性存储器中选择性地应用程序抑制方案
公开(公告)号：US07295478B2
公开(公告)日：2007-11-13
申请号：US11127743
申请日：2005-05-12
申请人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Jan Hemink , Ken Oowada , Jian Chen , Geoffrey S. Gongwer
发明人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Jan Hemink , Ken Oowada , Jian Chen , Geoffrey S. Gongwer
IPC分类号： G11C7/00
CPC分类号： G11C16/3418
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。基于正在编程的字线选择程序禁止方案。已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。可以基于系统的温度来选择程序禁止方案。

3. 发明申请

US20110235423A1 VERIFICATION PROCESS FOR NON-VOLATILE STORAGE 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：US20110235423A1
公开(公告)日：2011-09-29
申请号：US13154810
申请日：2011-06-07
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

4. 发明授权

US07978527B2 Verification process for non-volatile storage 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：US07978527B2
公开(公告)日：2011-07-12
申请号：US12132452
申请日：2008-06-03
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/06
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

5. 发明申请

US20090296475A1 VERIFICATION PROCESS FOR NON-VOLATILE STORAGE 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：US20090296475A1
公开(公告)日：2009-12-03
申请号：US12132452
申请日：2008-06-03
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

6. 发明授权

US08218367B2 Verification process for non-volatile storage 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：US08218367B2
公开(公告)日：2012-07-10
申请号：US13154810
申请日：2011-06-07
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/06
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

7. 发明授权

US07355889B2 Method for programming non-volatile memory with reduced program disturb using modified pass voltages 有权
标题翻译：使用修改的通过电压对具有减少的编程干扰的非易失性存储器进行编程的方法
公开(公告)号：US07355889B2
公开(公告)日：2008-04-08
申请号：US11313023
申请日：2005-12-19
申请人： Gerrit Jan Hemink , Ken Oowada
发明人： Gerrit Jan Hemink , Ken Oowada
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3459 , G11C2211/5621
摘要： Non-volatile storage elements are programmed in a manner that reduces program disturb by using modified pass voltages. In particular, during the programming of a selected storage element associated with a selected word line, a higher pass voltage is applied to word lines associated with previously programmed non-volatile storage elements in the set than to word lines associated with unprogrammed and/or partly programmed non-volatile storage elements in the set. The pass voltage is sufficiently high to balance the channel potentials on the source and drain sides of the selected word line and/or to reduce leakage of charge between the boosted channel regions. Optionally, an isolation region is formed between the boosted channel regions by applying a reduced voltage on one or more word lines between the selected word line and the word lines that receive the higher pass voltage.
摘要翻译：非易失性存储元件以通过使用修改的通过电压来减少编程干扰的方式被编程。特别地，在与所选择的字线相关联的所选择的存储元件的编程期间，将较高的通过电压施加到与组中的先前编程的非易失性存储元件相关联的字线，而不是与未编程和/或部分相关联的字线在集合中编程的非易失性存储元件。通过电压足够高以平衡所选字线的源极和漏极侧上的沟道电位和/或减小在升压的沟道区之间的电荷泄漏。可选地，通过在所选择的字线和接收较高通过电压的字线之间的一个或多个字线上施加降低的电压，在升压的沟道区之间形成隔离区。

8. 发明授权

US07672165B2 Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices 有权
标题翻译：用于主动升压以最小化闪存器件的相邻栅极之间的电容耦合效应的方法
公开(公告)号：US07672165B2
公开(公告)日：2010-03-02
申请号：US12031640
申请日：2008-02-14
申请人： Tuan D Pham , Masaaki Higashitani , Hao Fang Fang , Gerrit Jan Hemink
发明人： Tuan D Pham , Masaaki Higashitani , Hao Fang Fang , Gerrit Jan Hemink
IPC分类号： G11C16/00
CPC分类号： G11C16/0483 , H01L23/5222 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , H01L2924/0002 , H01L2924/00
摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.
摘要翻译： NAND闪存器件采用独特的增压板设计。升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在门中的电荷所需的电压电平。升压板还屏蔽浮动栅极之间的不必要的耦合。自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。因此，根据本发明可以实现更紧凑和可靠的存储器件。

9. 发明申请

US20130223155A1 TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储的验证操作期间基于温度的补偿
公开(公告)号：US20130223155A1
公开(公告)日：2013-08-29
申请号：US13403934
申请日：2012-02-23
申请人： Ken Oowada , Yingda Dong , Gerrit Jan Hemink , Man Lung Mui , Hao Nguyen , Seungpil Lee , Jong Park , Fanglin Zhang
发明人： Ken Oowada , Yingda Dong , Gerrit Jan Hemink , Man Lung Mui , Hao Nguyen , Seungpil Lee , Jong Park , Fanglin Zhang
IPC分类号： G11C16/10
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

10. 发明申请

US20080279007A1 BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING 有权
标题翻译：使用通道隔离开关来促进非易失性存储
公开(公告)号：US20080279007A1
公开(公告)日：2008-11-13
申请号：US11745082
申请日：2007-05-07
申请人： Yingda Dong , Jeffrey W. Lutze , Shih-Chung Lee , Gerrit Jan Hemink , Ken Oowada
发明人： Yingda Dong , Jeffrey W. Lutze , Shih-Chung Lee , Gerrit Jan Hemink , Ken Oowada
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/0483
摘要： Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.
摘要翻译：在非易失性存储器中通过防止所选择的NAND串中的源极升压来减少编程干扰。使用包括隔离字线的自增强模式。禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

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