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1. 发明申请

US20080019180A1 Selective Program Voltage Ramp Rates in Non-Volatile Memory 有权
标题翻译：非易失性存储器中的选择性编程电压斜坡率
公开(公告)号：US20080019180A1
公开(公告)日：2008-01-24
申请号：US11866261
申请日：2007-10-02
申请人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Hemink , Ken Oowada , Jian Chen , Geoffrey Gongwer
发明人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Hemink , Ken Oowada , Jian Chen , Geoffrey Gongwer
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/3418
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。基于正在编程的字线选择程序禁止方案。已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。可以基于系统的温度来选择程序禁止方案。

2. 发明申请

US20060279990A1 Selective application of program inhibit schemes in non-volatile memory 有权
标题翻译：在非易失性存储器中选择性地应用程序抑制方案
公开(公告)号：US20060279990A1
公开(公告)日：2006-12-14
申请号：US11127743
申请日：2005-05-12
申请人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Hemink , Ken Oowada , Jian Chen , Geoffrey Gongwer
发明人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Hemink , Ken Oowada , Jian Chen , Geoffrey Gongwer
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。基于正在编程的字线选择程序禁止方案。已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。可以基于系统的温度来选择程序禁止方案。

3. 发明申请

US20060239079A1 Noise Reduction Technique for Transistors and Small Devices Utilizing an Episodic Agitation 有权
标题翻译：使用剧集搅拌的晶体管和小型设备的降噪技术
公开(公告)号：US20060239079A1
公开(公告)日：2006-10-26
申请号：US11426082
申请日：2006-06-23
申请人： Nima Mokhlesi , Daniel Guterman , Geoffrey Gongwer
发明人： Nima Mokhlesi , Daniel Guterman , Geoffrey Gongwer
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/0458 , G11C16/26
摘要： The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.
摘要翻译：本发明提供了用于通过在读取过程的一部分中对电池的一些或多个端子施加情景搅动（例如，时变电压）来减少读取非易失性存储装置中固有噪声的量的方法。本发明的各个方面也扩展到超出非易失性存储器的设备。根据本发明的一个方面，除了作为读取过程的一部分而施加到单元的正常电压电平之外，还对电池施加时变电压。一组示例性实施例在读取过程的信号积分时间之前或期间将单个或多组交流电应用于浮动栅极存储器单元的一个或多个端子。在其他实施例中，可重复的其他可再现的外部或内部搅拌以及其平均效应（从一个积分时间到下一个积分时间）保持足够恒定，以便具有净噪声降低效果。

4. 发明申请

US20050169051A1 Writable tracking cells 有权
标题翻译：可追踪单元格
公开(公告)号：US20050169051A1
公开(公告)日：2005-08-04
申请号：US11064529
申请日：2005-02-22
申请人： Shahzad Khalid , Daniel Guterman , Geoffrey Gongwer , Richard Simko , Kevin Conley
发明人： Shahzad Khalid , Daniel Guterman , Geoffrey Gongwer , Richard Simko , Kevin Conley
IPC分类号： G11C7/06 , G11C7/14 , G11C11/34 , G11C11/56 , G11C27/00
CPC分类号： G11C7/14 , G11C7/06 , G11C11/5642 , G11C27/005 , G11C2211/5634
摘要： The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset. In one embodiment, two populations each consisting of multiple tracking cells are associated with two logic levels of the multi-bit cell. In an analog implementation, the user cells are read directly using the analog threshold values of the tracking cell populations without their first being translated to digital values. A set of alternate embodiments provide for using different voltages and/or timing for the writing of tracking cells to provide less uncertainty in the tracking cells' final written thresholds.
摘要翻译：本发明提出了使用可写跟踪单元的几种技术。为存储器的每个写入块提供多个跟踪单元。每当相关联的写入块的用户单元被优选地同时使用相同的固定的全局参考电平来写入时，这些单元被重新编程，以设置跟踪和用户单元编程的阈值。每次读取用户单元时，读取跟踪单元的阈值电压，并且这些阈值用于确定用户单元的存储的逻辑电平。在一组实施例中，一个或多个跟踪单元的群体与多状态存储器的不同逻辑电平相关联。这些跟踪单元群可以仅提供逻辑电平的子集。基于该子集，针对所有逻辑电平导出用于转换阈值电压的读取点。在一个实施例中，由多个跟踪单元组成的两个群组与多位单元的两个逻辑电平相关联。在模拟实现中，使用跟踪单元格群体的模拟阈值直接读取用户单元，而不首先将其转换为数字值。一组替代实施例提供使用不同的电压和/或定时来跟踪单元的写入，以便在跟踪单元的最终写入阈值中提供较小的不确定性。

5. 发明授权

US07139465B2 Non-volatile memory with improved programming and method therefor 有权
公开(公告)号：US07139465B2
公开(公告)日：2006-11-21
申请号：US11126044
申请日：2005-05-09
申请人： Geoffrey Gongwer , Daniel C. Guterman
发明人： Geoffrey Gongwer , Daniel C. Guterman
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3481 , G11C2211/5621
摘要： Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.

6. 发明申请

US20060015677A1 Symbol frequency leveling in a storage system 有权
标题翻译：存储系统中的符号频率调平
公开(公告)号：US20060015677A1
公开(公告)日：2006-01-19
申请号：US11201007
申请日：2005-08-09
申请人： Geoffrey Gongwer , Stephen Gross
发明人： Geoffrey Gongwer , Stephen Gross
IPC分类号： G06F12/00
CPC分类号： H03M5/00 , H03M7/40
摘要： Methods and apparatus for transforming data into a format which may be efficiently stored in a non-volatile memory are disclosed. According to one aspect of the present invention, a method for storing information of a first data format in a memory system includes generating statistics associated with the first data format, and transforming the information from the first data format to a second data format using the statistics. Once the information is transformed into the second data format, the information is stored into a memory. Storing the information in the second data format in the memory includes storing an identifier that identifies a transformation used to transform the information to the second data format. In one embodiment, costs associated with storing the information in the second data format are less than or equal to costs associated with storing the information in the first data format.
摘要翻译：公开了将数据转换成可以有效地存储在非易失性存储器中的格式的方法和装置。根据本发明的一个方面，一种用于将第一数据格式的信息存储在存储器系统中的方法包括生成与第一数据格式相关联的统计信息，以及使用统计信息将信息从第一数据格式转换为第二数据格式。一旦信息被转换成第二数据格式，信息被存储到存储器中。以第二数据格式存储在存储器中的信息包括存储识别用于将信息变换为第二数据格式的变换的标识符。在一个实施例中，与以第二数据格式存储信息相关联的成本小于或等于与以第一数据格式存储信息相关联的成本。

7. 发明申请

US20070226434A1 DATA RECOVERY IN A MEMORY SYSTEM USING TRACKING CELLS 有权
标题翻译：使用跟踪单元的存储器系统中的数据恢复
公开(公告)号：US20070226434A1
公开(公告)日：2007-09-27
申请号：US11752024
申请日：2007-05-22
申请人： Daniel Guterman , Stephen Gross , Shahzad Khalid , Geoffrey Gongwer
发明人： Daniel Guterman , Stephen Gross , Shahzad Khalid , Geoffrey Gongwer
IPC分类号： G06F12/00
CPC分类号： G11C16/26 , G11C11/5621 , G11C16/349
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.
摘要翻译：在存储器系统中使用跟踪单元来改善读取过程。跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。

8. 发明申请

US20050057979A1 Noise reduction technique for transistors and small devices utilizing an episodic agitation 有权
公开(公告)号：US20050057979A1
公开(公告)日：2005-03-17
申请号：US10976692
申请日：2004-10-28
申请人： Nima Mokhlesi , Daniel Guterman , Geoffrey Gongwer
发明人： Nima Mokhlesi , Daniel Guterman , Geoffrey Gongwer
IPC分类号： G11C16/06 , G11C11/56 , G11C16/04 , G11C16/26 , G11C7/00
CPC分类号： G11C11/5642 , G11C16/0458 , G11C16/26
摘要： The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

9. 发明授权

US06738289B2 Non-volatile memory with improved programming and method therefor 有权
公开(公告)号：US06738289B2
公开(公告)日：2004-05-18
申请号：US09793370
申请日：2001-02-26
申请人： Geoffrey Gongwer , Daniel C. Guterman
发明人： Geoffrey Gongwer , Daniel C. Guterman
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3481 , G11C2211/5621
摘要： Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.

10. 发明申请

US20070147168A1 METHODS FOR WRITING NON-VOLATILE MEMORIES FOR INCREASED ENDURANCE 有权
标题翻译：撰写非易失性存储器以增加耐用性的方法
公开(公告)号：US20070147168A1
公开(公告)日：2007-06-28
申请号：US11321217
申请日：2005-12-28
申请人： Yosi Pinto , Geoffrey Gongwer , Oren Honen
发明人： Yosi Pinto , Geoffrey Gongwer , Oren Honen
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C16/349 , G11C16/3495
摘要： A memory system that incorporates methods of amplifying the lifetime of a counter made up of memory elements, such as EEPROM cells, having finite endurance. A relatively small memory made up of a number of individually accessible write segments, where, depending on the embodiment, each write segment is made up of a single memory cell or a small number of cells (e.g., a byte). A count is encoded so that it is distributed across a number of fields, each associated with one of the write segments, such that as the count is incremented only a single field (or, in the single bit embodiments, occasionally more than one field) is changed and that these changes are evenly distributed across the fields. The changed field is then written to the corresponding segment, while the other write segments are unchanged. Consequently, the number of rewrites to a given write segment is decreased, and the lifetime correspondingly increased, by a factor corresponding to the number of write segments used.
摘要翻译：一种存储系统，其包含放大由具有有限耐久性的诸如EEPROM单元之类的存储元件组成的计数器的寿命的方法。由多个单独访问的写入段构成的相对小的存储器，其中根据实施例，每个写入段由单个存储器单元或少量单元（例如，一个字节）组成。计数被编码，使得其分布在多个字段中，每个字段与写入段之一相关联，使得当计数仅增加一个字段（或者在单个实施例中，偶尔地多于一个字段）改变了这些变化是均匀地分布在各个领域。然后将更改的字段写入相应的段，而其他写段不变。因此，给定写入段的重写次数减少，并且寿命相应地增加了与所使用的写入段数相对应的因子。

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