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31. 发明授权

US06562725B2 Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide etch stop layers 有权
标题翻译：采用氮化碳化硅和非氮化碳化硅蚀刻停止层的双镶嵌结构
公开(公告)号：US06562725B2
公开(公告)日：2003-05-13
申请号：US09899420
申请日：2001-07-05
申请人： Ming-Hsing Tsai , Ching-Hua Hsieh , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Ching-Hua Hsieh , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L2100
CPC分类号： H01L21/76829 , H01L21/31116 , H01L21/314 , H01L21/7681 , H01L21/76834
摘要： Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a first etch stop layer formed of a first material and a second etch stop layer formed of a second material. One of the first material and the second material is a non-nitrogenated silicon carbide material and the other of the first material and the second material is a nitrogenated silicon carbide material. By employing the first material and the second material, there may be etched completely through the first etch stop layer to reach a contact region formed there beneath while not etching completely through the second etch stop layer to reach a first dielectric layer formed there beneath.
摘要翻译：在用于在微电子制造中形成双镶嵌孔的双镶嵌方法中，采用由第一材料形成的第一蚀刻停止层和由第二材料形成的第二蚀刻停止层。第一材料和第二材料之一是非氮化碳化硅材料，第一材料和第二材料中的另一种是氮化碳化硅材料。通过使用第一材料和第二材料，可以完全蚀刻通过第一蚀刻停止层以到达其下方形成的接触区域，而不完全蚀刻通过第二蚀刻停止层，以到达在其下方形成的第一介电层。

32. 发明授权

US06224737B1 Method for improvement of gap filling capability of electrochemical deposition of copper 有权
标题翻译：改进铜电化学沉积间隙填充能力的方法
公开(公告)号：US06224737B1
公开(公告)日：2001-05-01
申请号：US09377540
申请日：1999-08-19
申请人： Ming-Hsing Tsai , Wen-Jye Tsai , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Wen-Jye Tsai , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： C25D502
CPC分类号： H01L21/76877 , C25D3/38 , C25D5/48 , C25D7/123 , H01L21/2885 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure having a trench formed therein is provided. The semiconductor structure may be a substrate with an overlying interlevel metal dielectric layer having the trench. A voltage is applied to the trenched semiconductor inducing a bias field where there is a first field proximate the trench bottom and a second field, greater than the first field, proximate the trench's upper side walls and the semiconductor upper surface proximate the trench. The semiconductor structure is placed into an electroplating solution containing a predetermined concentration of brighteners and levelers. Because of the induced bias field, the brightener concentration is greater proximate the trench bottom and the leveler concentration is greater the trench's upper side walls and the semiconductor upper surface proximate the trench. A copper layer having a predetermined thickness is then electrolytically deposited within the trench in a “bottom-up” fashion and blanket fills the upper surface of the semiconductor structure. The structure may then be planarized by CMP to create a planarized copper filled trench.
摘要翻译：提供具有形成在其中的沟槽的半导体结构。半导体结构可以是具有具有沟槽的上覆层间金属介电层的衬底。电压被施加到沟槽半导体，其诱导偏置场，其中存在靠近沟槽底部的第一场和大于第一场，接近沟槽的上侧壁和靠近沟槽的半导体上表面的第二场。将半导体结构放入含有预定浓度的增白剂和矫直剂的电镀溶液中。由于感应偏压场，光滑剂浓度在沟槽底部附近较大，并且矫直剂浓度大于沟槽的上侧壁和接近沟槽的半导体上表面。然后将具有预定厚度的铜层以“自下而上”的方式电解沉积在沟槽内，并且覆盖填充半导体结构的上表面。然后可以通过CMP平面化该结构以产生平坦化的铜填充沟槽。

33. 发明申请

US20110024908A1 LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE 有权
标题翻译：低电阻高可靠性接触半导体器件的金属线结构
公开(公告)号：US20110024908A1
公开(公告)日：2011-02-03
申请号：US12845852
申请日：2010-07-29
申请人： Hsiang-Huan Lee , Ming Han Lee , Ming-Shih Yeh , Chen-Hua Yu , Shau-Lin Shue
发明人： Hsiang-Huan Lee , Ming Han Lee , Ming-Shih Yeh , Chen-Hua Yu , Shau-Lin Shue
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53238 , H01L21/28562 , H01L21/76846 , H01L21/76867 , H01L21/76873 , H01L21/76883 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.
摘要翻译：上述结构和方法提供了提高互连可靠性和电阻率的机制。通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。

34. 发明申请

US20100151639A1 METHOD FOR MAKING A THERMALLY-STABLE SILICIDE 审中-公开
标题翻译：制备耐热硅酮的方法
公开(公告)号：US20100151639A1
公开(公告)日：2010-06-17
申请号：US12712518
申请日：2010-02-25
申请人： Shau-Lin Shue , Chen-Hua Yu , Cheng-Tung Lin , Chii-Ming Wu , Shih-Wei Chou , Gin Jei Wang , CP Lo , Chih-Wei Chang
发明人： Shau-Lin Shue , Chen-Hua Yu , Cheng-Tung Lin , Chii-Ming Wu , Shih-Wei Chou , Gin Jei Wang , CP Lo , Chih-Wei Chang
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/665 , H01L21/76243 , H01L29/785
摘要： Provided is a method of fabrication a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, the gate structure including a gate dielectric and a gate electrode disposed over the gate dielectric, forming source/drain regions in the semiconductor substrate at either side of the gate structure, forming a metal layer over the semiconductor substrate and the gate structure, the metal layer including a refractory metal layer or a refractory metal compound layer; forming an alloy layer over the metal layer; and performing an annealing thereby forming metal alloy silicides over the gate structure and the source/drain regions, respectively.
摘要翻译：提供一种制造半导体器件的方法，其包括提供半导体衬底，在衬底上形成栅极结构，栅极结构包括栅极电介质和设置在栅极电介质上的栅电极，在半导体衬底中形成源极/漏极区域在栅极结构的任一侧，在半导体衬底和栅极结构之上形成金属层，金属层包括难熔金属层或难熔金属化合物层; 在所述金属层上形成合金层; 并进行退火，从而分别在栅极结构和源极/漏极区域上形成金属合金硅化物。

35. 发明申请

US20090117731A1 SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译：半导体互连结构及其制造方法
公开(公告)号：US20090117731A1
公开(公告)日：2009-05-07
申请号：US11934005
申请日：2007-11-01
申请人： Chen-Hua Yu , Shau-Lin Shue , Chien-Hsueh Shih , Ming-Shih Yeh , Ming-Han Lee
发明人： Chen-Hua Yu , Shau-Lin Shue , Chien-Hsueh Shih , Ming-Shih Yeh , Ming-Han Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L21/76856 , H01L21/76867 , H01L21/76873 , H01L21/76877 , H01L2221/1089
摘要： A semiconductor interconnection structure is manufactured as follows. First, a substrate with a first dielectric layer and a second dielectric layer is formed. Subsequently, an opening is formed in the second dielectric layer. A thin metal layer and a seed layer are formed in sequence on the surface of the second dielectric layer in the opening, wherein the metal layer comprises at least one metal species having phase segregation property of a second conductor. The wafer of the substrate is subjected to a thermal treatment, by which most of the metal species in the metal layer at a bottom of the opening is diffused to a top surface of the second conductor to form a metal-based oxide layer. Afterwards, the wafer is subjected to planarization, so as to remove the second conductor outside the opening.
摘要翻译：如下制造半导体互连结构。首先，形成具有第一介电层和第二介质层的基板。随后，在第二电介质层中形成开口。在开口中的第二电介质层的表面上依次形成薄金属层和种子层，其中金属层包含至少一种具有第二导体的相分离特性的金属物质。对基板的晶片进行热处理，通过该热处理，开口底部的金属层中的大部分金属物质扩散到第二导体的顶表面，形成金属基氧化物层。然后，对晶片进行平面化处理，以便将开口外的第二导体移除。

36. 发明授权

US07354856B2 Method for forming dual damascene structures with tapered via portions and improved performance 有权
标题翻译：用于形成具有锥形通孔部分的双镶嵌结构和改进的性能的方法
公开(公告)号：US07354856B2
公开(公告)日：2008-04-08
申请号：US11071104
申请日：2005-03-04
申请人： Ming-Shih Yeh , Ming-Hsing Tsai , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Shih Yeh , Ming-Hsing Tsai , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/44
CPC分类号： H01L21/76804 , H01L21/31144 , H01L21/314 , H01L21/76808 , Y10S438/978
摘要： The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer is formed above the conductive layer. An etching stop layer is formed above the protective layer and the first insulating layer. A second insulating layer is formed above the etching stop layer. A first patterned photoresist layer is formed above the second insulating layer, the first patterned photoresist layer having a first pattern. The first pattern is etched into the second insulating layer and the etching stop layer to form a first opening. A via plug is filled at least partially in the first opening. An anti-reflective coating (ARC) layer is formed above the second insulating layer. A second patterned photoresist layer is formed above the ARC layer, the second photoresist layer having a second pattern. The second pattern is etched into portions of the via plug, second insulation layer, and the ARC layer to form a second opening, wherein a substantially tapered sidewall portion is formed at the interface of the first and second openings.
摘要翻译：提供了具有改进的性能，特别但非限制性的双镶嵌结构的镶嵌结构的制造。在一个实施例中，具有导电层的衬底形成在第一绝缘层中。在导电层上形成保护层。在保护层和第一绝缘层上方形成蚀刻停止层。在蚀刻停止层上形成第二绝缘层。第一图案化光致抗蚀剂层形成在第二绝缘层之上，第一图案化光致抗蚀剂层具有第一图案。将第一图案蚀刻到第二绝缘层和蚀刻停止层中以形成第一开口。通孔塞至少部分地填充在第一开口中。在第二绝缘层上方形成抗反射涂层（ARC）层。第二图案化光致抗蚀剂层形成在ARC层上方，第二光致抗蚀剂层具有第二图案。第二图案被蚀刻到通孔塞，第二绝缘层和ARC层的部分中以形成第二开口，其中在第一和第二开口的界面处形成大致锥形的侧壁部分。

37. 发明申请

US20080009133A1 Sidewall Coverage For Copper Damascene Filling 有权
标题翻译：铜镶嵌填料的侧壁覆盖
公开(公告)号：US20080009133A1
公开(公告)日：2008-01-10
申请号：US11860639
申请日：2007-09-25
申请人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
发明人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76862 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L2221/1089
摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.
摘要翻译：描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。具体应用是用铜填充沟槽以形成镶嵌线。首先，通过PVD将种子层沉积在孔或沟槽中。然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

38. 发明授权

US07250683B2 Method to solve via poisoning for porous low-k dielectric 有权
标题翻译：解决多孔低介电常数中毒的方法
公开(公告)号：US07250683B2
公开(公告)日：2007-07-31
申请号：US11056758
申请日：2005-02-11
申请人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L2221/1063
摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.
摘要翻译：公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

39. 发明申请

US20060138668A1 Passivation structure for semiconductor devices 审中-公开
标题翻译：半导体器件钝化结构
公开(公告)号：US20060138668A1
公开(公告)日：2006-06-29
申请号：US11023296
申请日：2004-12-27
申请人： Hung-Wen Su , Chien-Hsueh Shih , Minghsing Tsai , Shau-Lin Shue , Chen-Hua Yu
发明人： Hung-Wen Su , Chien-Hsueh Shih , Minghsing Tsai , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L23/06
CPC分类号： H01L23/53238 , H01L21/288 , H01L21/76846 , H01L21/76849 , H01L21/76865 , H01L2924/0002 , H01L2924/00
摘要： A system and method for providing a passivation structure for semiconductor devices is provided. In an embodiment, the passivation structure comprises a first barrier layer and a second barrier layer, wherein the second barrier layer may comprise a material, such as cobalt and/or nickel, that is less pure than the first barrier layer. In another embodiment, a single gradient barrier layer is formed. In this embodiment the single gradient barrier layer exhibits a greater pure conductive material, such as cobalt and/or nickel, nearer the conductive line than near the surface.
摘要翻译：提供了一种用于提供半导体器件的钝化结构的系统和方法。在一个实施例中，钝化结构包括第一阻挡层和第二阻挡层，其中第二阻挡层可以包括比第一阻挡层更纯的材料，例如钴和/或镍。在另一个实施例中，形成单个梯度阻挡层。在该实施例中，单个梯度阻挡层表现出比在表面附近更靠近导电线的较高纯度的导电材料，例如钴和/或镍。

40. 发明授权

US06342448B1 Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process 有权
标题翻译：在铜镶嵌工艺中制造对低k电介质层的屏障粘附的方法
公开(公告)号：US06342448B1
公开(公告)日：2002-01-29
申请号：US09583401
申请日：2000-05-31
申请人： Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
发明人： Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L21/28568 , H01L21/76807 , H01L21/76873
摘要： A method for forming an improved TaN copper barrier for a copper damascene process is described which has improved adhesion to low-k dielectric layers and also improves the wetting of a copper seed layer deposited over it thereby improving the structure of the copper seed layer which is critical to achieving uniform, high quality electrochemical copper deposition. The copper barrier is a composite structure having an lower thin Ta rich TaN portion which mixes into and reacts with the surface of the low-k dielectric layer, forming a strongly bonded transition layer between the low-k material and the remaining portion of the barrier layer. The presence of the transition layer causes compressive film stress rather than tensile stress as found in the conventional TaN barrier. As a result, the barrier layer does not delaminate from the low-k layer during subsequent processing. A second thick central portion of the barrier layer is formed of stoichiometric TaN which benefits subsequent CMP of the copper damascene structure. An upper thin Ta portion improves barrier wetting to the copper seed layer. The three sections of the laminar barrier are sequentially deposited in a single pumpdown operation by IMP sputtering from a Ta target.
摘要翻译：描述了一种用于形成用于铜镶嵌工艺的改进的TaN铜阻挡层的方法，其具有改善的对低k电介质层的粘附性，并且还改善了沉积在其上的铜籽晶层的润湿，从而改善了铜籽晶层的结构，对于实现均匀，高质量的电化学铜沉积至关重要。铜屏障是具有较低的Ta Ta薄部分的复合结构，其混合并与低k电介质层的表面反应，在低k材料与阻挡层的剩余部分之间形成牢固结合的过渡层层。过渡层的存在导致压缩膜应力而不是常规TaN阻挡层中的拉伸应力。结果，在随后的处理期间，阻挡层不会从低k层分层。阻挡层的第二厚中心部分由化学计量的TaN形成，这有利于铜镶嵌结构的后续CMP。上部薄的Ta部分改善了对铜种子层的屏障润湿。层状阻挡层的三个部分通过来自Ta靶的IMP溅射在单次抽运操作中依次沉积。

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