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1. 发明申请

US20050170648A1 Method to solve via poisoning for porous low-k dielectric 有权
公开(公告)号：US20050170648A1
公开(公告)日：2005-08-04
申请号：US11056758
申请日：2005-02-11
申请人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L2221/1063
摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

2. 发明授权

US07250683B2 Method to solve via poisoning for porous low-k dielectric 有权
标题翻译：解决多孔低介电常数中毒的方法
公开(公告)号：US07250683B2
公开(公告)日：2007-07-31
申请号：US11056758
申请日：2005-02-11
申请人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L2221/1063
摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.
摘要翻译：公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

3. 发明授权

US06342448B1 Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process 有权
标题翻译：在铜镶嵌工艺中制造对低k电介质层的屏障粘附的方法
公开(公告)号：US06342448B1
公开(公告)日：2002-01-29
申请号：US09583401
申请日：2000-05-31
申请人： Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
发明人： Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L21/28568 , H01L21/76807 , H01L21/76873
摘要： A method for forming an improved TaN copper barrier for a copper damascene process is described which has improved adhesion to low-k dielectric layers and also improves the wetting of a copper seed layer deposited over it thereby improving the structure of the copper seed layer which is critical to achieving uniform, high quality electrochemical copper deposition. The copper barrier is a composite structure having an lower thin Ta rich TaN portion which mixes into and reacts with the surface of the low-k dielectric layer, forming a strongly bonded transition layer between the low-k material and the remaining portion of the barrier layer. The presence of the transition layer causes compressive film stress rather than tensile stress as found in the conventional TaN barrier. As a result, the barrier layer does not delaminate from the low-k layer during subsequent processing. A second thick central portion of the barrier layer is formed of stoichiometric TaN which benefits subsequent CMP of the copper damascene structure. An upper thin Ta portion improves barrier wetting to the copper seed layer. The three sections of the laminar barrier are sequentially deposited in a single pumpdown operation by IMP sputtering from a Ta target.
摘要翻译：描述了一种用于形成用于铜镶嵌工艺的改进的TaN铜阻挡层的方法，其具有改善的对低k电介质层的粘附性，并且还改善了沉积在其上的铜籽晶层的润湿，从而改善了铜籽晶层的结构，对于实现均匀，高质量的电化学铜沉积至关重要。铜屏障是具有较低的Ta Ta薄部分的复合结构，其混合并与低k电介质层的表面反应，在低k材料与阻挡层的剩余部分之间形成牢固结合的过渡层层。过渡层的存在导致压缩膜应力而不是常规TaN阻挡层中的拉伸应力。结果，在随后的处理期间，阻挡层不会从低k层分层。阻挡层的第二厚中心部分由化学计量的TaN形成，这有利于铜镶嵌结构的后续CMP。上部薄的Ta部分改善了对铜种子层的屏障润湿。层状阻挡层的三个部分通过来自Ta靶的IMP溅射在单次抽运操作中依次沉积。

4. 发明授权

US07193327B2 Barrier structure for semiconductor devices 有权
标题翻译：半导体器件的阻挡结构
公开(公告)号：US07193327B2
公开(公告)日：2007-03-20
申请号：US11042396
申请日：2005-01-25
申请人： Chen-Hua Yu , Shing-Chyang Pan , Shau-Lin Shue , Ching-Hua Hsieh , Cheng-Lin Huang , Hsien-Ming Lee , Jing-Cheng Lin
发明人： Chen-Hua Yu , Shing-Chyang Pan , Shau-Lin Shue , Ching-Hua Hsieh , Cheng-Lin Huang , Hsien-Ming Lee , Jing-Cheng Lin
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53295 , H01L21/76805 , H01L21/76844 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.
摘要翻译：提供具有独特的阻挡层结构的电介质层中的开口。在一个实施例中，开口是通孔和沟槽。可以形成阻挡层，其可以包括一个或多个阻挡层，使得阻挡层的厚度在沟槽的底部和电介质层的顶部之间的大致中间的侧壁与屏障的厚度之比沿着沟槽底部的层大于约0.55。在另一个实施例中，沿着沟槽底部和电介质层的顶部之间大约中间的侧壁的阻挡层的厚度与通孔底部的阻挡层的厚度之比大于约1.0。潜在的导电层可以凹入。

5. 发明申请

US20060163746A1 Barrier structure for semiconductor devices 有权
标题翻译：半导体器件的阻挡结构
公开(公告)号：US20060163746A1
公开(公告)日：2006-07-27
申请号：US11042396
申请日：2005-01-25
申请人： Chen-Hua Yu , Shing-Chyang Pan , Shau-Lin Shue , Ching-Hua Hsieh , Cheng-Lin Huang , Hsien-Ming Lee , Jing-Cheng Lin
发明人： Chen-Hua Yu , Shing-Chyang Pan , Shau-Lin Shue , Ching-Hua Hsieh , Cheng-Lin Huang , Hsien-Ming Lee , Jing-Cheng Lin
IPC分类号： H01L23/48
CPC分类号： H01L23/53295 , H01L21/76805 , H01L21/76844 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.
摘要翻译：提供具有独特的阻挡层结构的电介质层中的开口。在一个实施例中，开口是通孔和沟槽。可以形成阻挡层，其可以包括一个或多个阻挡层，使得阻挡层的厚度在沟槽的底部和电介质层的顶部之间的大致中间的侧壁与屏障的厚度之比沿着沟槽底部的层大于约0.55。在另一个实施例中，沿着沟槽底部和电介质层的顶部之间大约中间的侧壁的阻挡层的厚度与通孔底部的阻挡层的厚度之比大于约1.0。潜在的导电层可以凹入。

6. 发明授权

US06878615B2 Method to solve via poisoning for porous low-k dielectric 失效
标题翻译：解决多孔低介电常数中毒的方法
公开(公告)号：US06878615B2
公开(公告)日：2005-04-12
申请号：US09863224
申请日：2001-05-24
申请人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L2221/1063
摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.
摘要翻译：公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

7. 发明申请

US20070181434A1 Method and apparatus for fabricating metal layer 审中-公开
标题翻译：金属层制造方法及装置
公开(公告)号：US20070181434A1
公开(公告)日：2007-08-09
申请号：US11783245
申请日：2007-04-06
申请人： Hsien-Ming Lee , Jing-Cheng Lin , Shing-Chyang Pan , Ming-Hsing Tsai , Hung-Wen Su , Shih-Wei Chou , Shau-Lin Shue , Kuo-Wei Cheng , Ting-Chu Ko
发明人： Hsien-Ming Lee , Jing-Cheng Lin , Shing-Chyang Pan , Ming-Hsing Tsai , Hung-Wen Su , Shih-Wei Chou , Shau-Lin Shue , Kuo-Wei Cheng , Ting-Chu Ko
IPC分类号： C25D5/34 , H01L21/44 , C25D3/38
CPC分类号： H01L21/2885 , H01L21/76843 , H01L21/76861 , H01L21/76862 , H01L21/76873 , H01L21/76877
摘要： A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.
摘要翻译：电化学沉积（ECD）的方法在衬底上提供阻挡层和种子层。在将金属层电化学沉积在具有物理或化学表面处理工艺的电化学镀覆电池中之前，对基板的表面进行预处理。电化学镀覆电池被盖覆盖以防止电解质溶液的蒸发。电化学电镀单元包括具有提升密封件的衬底保持器组件，例如在提升密封件和衬底之间的接触角θ小于90°。衬底保持器组件包括在衬底的后侧的衬底卡盘。

8. 发明申请

US20060099802A1 Diffusion barrier for damascene structures 审中-公开
标题翻译：镶嵌结构的扩散屏障
公开(公告)号：US20060099802A1
公开(公告)日：2006-05-11
申请号：US10985149
申请日：2004-11-10
申请人： Jing-Cheng Lin , Shau-Lin Shue
发明人： Jing-Cheng Lin , Shau-Lin Shue
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/76826 , H01L21/76831
摘要： A semiconductor structure having a via formed in a dielectric layer is provided. The exposed pores of the dielectric material along the sidewalls of the via are partially or completely sealed. Thereafter, one or more barrier layers may be formed and the via may be filled with a conductive material. The barrier layers formed over the sealing layer exhibits a more continuous barrier layer. The pores may be partially or completely sealed by performing, for example, a plasma process in an argon environment.
摘要翻译：提供了具有形成在电介质层中的通孔的半导体结构。沿着通孔的侧壁的电介质材料的暴露的孔部分或完全密封。此后，可以形成一个或多个阻挡层，并且可以用导电材料填充通孔。形成在密封层之上的阻挡层表现出更连续的阻挡层。通过在氩气环境中进行例如等离子体处理，可以将孔部分或完全密封。

9. 发明申请

US20050266679A1 Barrier structure for semiconductor devices 审中-公开
标题翻译：半导体器件的阻挡结构
公开(公告)号：US20050266679A1
公开(公告)日：2005-12-01
申请号：US10995752
申请日：2004-11-23
申请人： Jing-Cheng Lin , Shau-Lin Shue
发明人： Jing-Cheng Lin , Shau-Lin Shue
IPC分类号： H01L21/768 , H01L21/4763 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76844 , H01L21/76865
摘要： A via having a unique barrier layer structure is provided. In an embodiment, a via is formed by forming a barrier layer in a via. The barrier layer along the bottom of the via is partially or completely removed, and the via is filled with a conductive material. In another embodiment, a first barrier layer is formed along the bottom and sidewalls of the via. Thereafter, the first barrier layer along the bottom of the via is partially or completely removed, and a second barrier layer is formed.
摘要翻译：提供具有独特的阻挡层结构的通孔。在一个实施例中，通孔在通孔中形成阻挡层而形成通孔。沿着通孔底部的阻挡层被部分地或完全去除，并且通孔用导电材料填充。在另一个实施例中，沿着通孔的底部和侧壁形成第一阻挡层。此后，沿通孔底部的第一阻挡层被部分地或完全地去除，形成第二阻挡层。

10. 发明申请

US20050239288A1 Sequential reducing plasma and inert plasma pre-treatment method for oxidizable conductor layer 有权
标题翻译：用于可氧化导体层的顺序还原等离子体和惰性等离子体预处理方法
公开(公告)号：US20050239288A1
公开(公告)日：2005-10-27
申请号：US10910182
申请日：2004-08-02
申请人： Chao-Hsien Peng , Jing-Cheng Lin , Ching-Hua Hsieh , Shau-Lin Shue
发明人： Chao-Hsien Peng , Jing-Cheng Lin , Ching-Hua Hsieh , Shau-Lin Shue
IPC分类号： H01L21/306 , H01L21/311 , H01L21/3213 , H01L21/44 , H01L21/768
CPC分类号： H01L21/76831 , H01L21/02046 , H01L21/32136 , H01L21/76807 , H01L21/76814 , H01L21/76838
摘要： A method for forming a barrier layer upon a copper containing conductor layer employs a hydrogen containing plasma treatment of the copper containing conductor layer followed by an argon plasma treatment of the copper containing conductor layer. The barrier layer may be formed employing a chemical vapor deposition method, such as an atomic layer deposition method. When the deposition method employs a metal and carbon containing source material, the two-step plasma pretreatment provides the barrier layer with enhanced electrical properties.
摘要翻译：在含铜导体层上形成阻挡层的方法采用含铜导体层的含氢等离子体处理，然后进行含铜导体层的氩等离子体处理。可以使用诸如原子层沉积方法的化学气相沉积方法形成阻挡层。当沉积方法采用含金属和碳的源材料时，两步等离子体预处理为阻挡层提供了增强的电性能。

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