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    • 31. 发明申请
    • Tiltable trailer hitch
    • 可倾倒的拖车搭便车
    • US20060284396A1
    • 2006-12-21
    • US11156247
    • 2005-06-17
    • Lane Smith
    • Lane Smith
    • B60D1/46
    • B60D1/665B60D1/46B60D1/465
    • A tiltable trailer hitch for assisting in the loading and unloading of a trailer. The hitch includes a shank adapted to be received within a conventional trailer hitch and a ballmount pivotally mounted on the shank. An adjustment bracket is carried by the shank and is adapted to attach a ballmount. The adjustment bracket defines cooperating pairs of first openings and cooperating pairs of second openings. The second openings are radially spaced apart about a first of the first openings. The first openings are radially spaced apart about a first of the second openings. The ballmount defines first and second openings for cooperatively receiving the first and second ballmount locking pins. The trailer is tilted up or down by moving the first and second ballmount locking pins up and down within the cooperating pairs of first and second openings.
    • 一种用于协助装载和卸载拖车的可倾斜拖车挂钩。 挂钩包括适于被接收在常规拖车搭接中的柄部和可枢转地安装在柄上的滚珠架。 调节支架由柄承载并适于附接球帽。 调节支架定义协作对的第一开口和配对的第二开口对。 第二开口围绕第一开口径向隔开。 第一开口围绕第一开口径向隔开。 第一和第二开口限定了第一和第二开口,用于协同地接收第一和第二安装座锁定销。 通过在协作的第一和第二开口对内上下移动第一和第二滚珠锁定销,拖车向上或向下倾斜。
    • 33. 发明申请
    • Frequency-lock detector
    • US20060176992A1
    • 2006-08-10
    • US11053365
    • 2005-02-08
    • Xingdong DiaMax OlsenLane Smith
    • Xingdong DiaMax OlsenLane Smith
    • H04L7/02
    • H04L7/033H03L7/095
    • A frequency-lock detector (FLD) adapted to register more than one target count per period of a target clock signal to generate a count value related to a frequency difference between the target clock signal and a reference clock signal. In various embodiments of the invention, this count registration is implemented by multiplying the target clock signal, discerning two or more phases of a signal, and/or organizing a count pipeline. In a representative embodiment, an FLD of the invention has a counter circuit and a control circuit. The counter circuit has (i) a frequency multiplier adapted to multiply the frequency of the target clock signal to generate a multiplied signal, (ii) two target counters adapted to register counts based on occurrences of two different phases of the accelerated signal to generate two auxiliary numbers, and (iii) a multiplexer adapted to select an appropriate one of the auxiliary numbers as the count value related to the frequency difference. The control circuit has a reference counter adapted to control, based on the reference clock signal, the count registration in the target counters and the value selection in the multiplexer.
    • 34. 发明申请
    • Phase interpolator having a phase jump
    • 相位内插器具有相位跳变
    • US20060133557A1
    • 2006-06-22
    • US11020021
    • 2004-12-22
    • Ronald FreymanVladimir SindalovskyLane Smith
    • Ronald FreymanVladimir SindalovskyLane Smith
    • H04L7/04
    • H03L7/07H03L7/0814H03L7/091H04L7/0025H04L7/0337
    • A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation region. A roaming tap interpolator is disclosed that shifts the interpolation curve in time in order to avoid the undesired artifacts in the interpolation curve. A roaming tap interpolator generally comprises a plurality of delay elements that delays a first signal to generate a plurality of interpolation regions each having an associated phase; a multiplexer to select one or more of the interpolation regions; and an interpolator to process the selected one or more of the interpolation regions to generate a second signal. In addition, according to the present invention, the roaming tap interpolator includes a delay unit that selectively delays one or more of the first signal and the second signal to generate an interpolation signal, the interpolation signal selectively having a first phase or a second phase.
    • 公开了一种基于漫游抽头内插器来产生相位控制数据的方法和装置。 本发明认识到,漫游抽头内插器在每个内插区域的边界处具有固有的非线性和不连续性。 公开了一种漫游抽头内插器,其在时间上偏移插值曲线,以避免插值曲线中的不需要的伪影。 漫游抽头内插器通常包括多个延迟元件,其延迟第一信号以产生每个具有相关联的相位的多个内插区域; 多路复用器,用于选择一个或多个插值区域; 以及内插器,用于处理所选择的一个或多个内插区域以产生第二信号。 此外,根据本发明,漫游抽头插值器包括延迟单元,其选择性地延迟第一信号和第二信号中的一个或多个以产生内插信号,该内插信号选择性地具有第一相位或第二相位。
    • 35. 发明申请
    • Transmit adaptive equalization using ordered sets
    • 使用有序集发送自适应均衡
    • US20060067387A1
    • 2006-03-30
    • US10955997
    • 2004-09-30
    • Ali AhmedRobert BrinkLane SmithRobert Snively
    • Ali AhmedRobert BrinkLane SmithRobert Snively
    • H04B1/38
    • H04B10/0779H04B10/07
    • In a communication system comprising first and second nodes, a transmit adaptive equalization technique is implemented utilizing ordered sets. The first and second nodes may communicate over a Fibre Channel link or other medium. The first and second nodes comprise respective transmitter and receiver pairs, with the transmitter of the first node configured for communication with the receiver of the second node and the receiver of the first node configured for communication with the transmitter of the second node. The first node is operative to receive from the second node information specifying an adjustment to one or more equalization parameters of the first node. The information is received in designated portions of one or more ordered sets transmitted from the second node to the first node in conjunction with initialization of a communication link between the first and second nodes. The first node adjusts the equalization parameter(s) in accordance with the received information.
    • 在包括第一和第二节点的通信系统中,利用有序集来实现发射自适应均衡技术。 第一和第二节点可以通过光纤通道链路或其他介质进行通信。 第一和第二节点包括相应的发射机和接收机对,其中第一节点的发射机被配置用于与第二节点的接收机进行通信,并且第一节点的接收机被配置用于与第二节点的发射机进行通信。 第一节点可操作以从第二节点接收指定对第一节点的一个或多个均衡参数的调整的信息。 结合第一和​​第二节点之间的通信链路的初始化,在从第二节点发送到第一节点的一个或多个有序集合的指定部分中接收信息。 第一节点根据接收到的信息调整均衡参数。
    • 36. 发明申请
    • CDR WITH SIGMA-DELTA NOISE-SHAPED CONTROL
    • CDR与SIGMA-DELTA噪声控制
    • US20120257693A1
    • 2012-10-11
    • US13081941
    • 2011-04-07
    • Vladimir SindalovskyLane SmithShawn Logan
    • Vladimir SindalovskyLane SmithShawn Logan
    • H04L27/06
    • H04L7/033H03L7/101H04L7/0004H04L25/03057
    • In described embodiments, a receiver includes a clock and data recovery (CDR) module with a voltage control oscillator (VCO) and a Sigma-Delta modulator in an integral loop control of the VCO. Providing finer resolution by the Sigma-Delta modulator reduces quantization noise in the integral control loop when compared to a loop without a Sigma-Delta modulator in the integral loop. Sigma-Delta modulation within the integral loop control of a VCO-based CDR reduces effective quantization of the VCO integral word control, allowing the proportional loop control compensation to i) reduce effective quantization of the VCO integral word control and, ii) enhance receiver jitter tolerance in presence of periodic-jitter, serial data whose frequency is offset from the nominal rate and serial data whose nominal frequency is modulated by a spread spectrum clock.
    • 在所描述的实施例中,接收机包括具有VCO的积分环路控制中的压控振荡器(VCO)和Σ-Δ调制器的时钟和数据恢复(CDR)模块。 当与积分环路中没有Σ-Δ调制器的环路相比时,通过Sigma-Delta调制器提供更精细的分辨率降低了积分控制环路中的量化噪声。 在基于VCO的CDR的积分环路控制中的Σ-Δ调制降低了VCO积分字控制的有效量化,允许比例环路控制补偿以减少VCO积分字控制的有效量化,以及ii)增强接收器抖动 存在频率偏离标称速率的串行数据的周期抖动的容限以及标称频率由扩频时钟调制的串行数据。
    • 38. 发明申请
    • Methods and apparatus for spread spectrum generation using a voltage controlled delay loop
    • 使用电压控制延迟环路进行扩频生成的方法和装置
    • US20060268958A1
    • 2006-11-30
    • US11141695
    • 2005-05-31
    • Vladimir SindalovskyLane SmithCraig Ziemer
    • Vladimir SindalovskyLane SmithCraig Ziemer
    • H04B1/00
    • H04B15/02H04B2215/067
    • Methods and apparatus are provided for generating a frequency with a predefined offset from a reference frequency. A spread spectrum generator circuit is disclosed that comprises a voltage controlled delay loop for generating a plurality of signals having a different phase; and at least one interpolator for processing at least two of the signals to generate an output signal having a phase between a phase of the at least two of the signals, wherein the output is varied between a phase of the at least two of the signals to generate the spread spectrum. A spread spectrum having a frequency lower than an applied clock signal is generated using a continuous phase delay increase and a spread spectrum having a frequency higher than the clock signal is generated using a continuous phase delay decrease.
    • 提供了用于产生具有与参考频率的预定义偏移的频率的方法和装置。 公开了一种扩频发生器电路,其包括用于产生具有不同相位的多个信号的电压控制延迟环路; 以及至少一个内插器,用于处理至少两个所述信号以产生具有所述至少两个所述信号的相位之间的相位的输出信号,其中所述输出在所述至少两个信号的相位之间变化 生成扩频。 使用连续的相位延迟增加来产生频率低于所施加的时钟信号的扩展频谱,并且使用连续的相位延迟减小产生具有高于时钟信号的频率的扩频。