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1. 发明申请

US20060114045A1 Voltage controlled delay loop with central interpolator 有权
标题翻译：具有中央插补器的电压控制延迟回路
公开(公告)号：US20060114045A1
公开(公告)日：2006-06-01
申请号：US10999889
申请日：2004-11-30
申请人： Ronald Freyman , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
发明人： Ronald Freyman , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises at least one delay element to generate at least two phases of a reference clock; a central interpolator for interpolating the at least two phases of the reference clock to generate an interpolated signal; and an input that injects the interpolated signal into a delay stage. The central interpolator provides a fine phase control. In addition, a coarse phase control can optionally be achieved by selectively injecting the interpolated signal into a given delay stage. A further voltage controlled delay loop is disclosed with coarse and fine phase control using a number of interpolators.
摘要翻译：公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。电压控制延迟环路产生具有相似频率和不同相位的时钟信号。电压控制延迟回路包括至少一个延迟元件以产生参考时钟的至少两个相位; 中央内插器，用于内插参考时钟的至少两个相位以产生内插信号; 以及将内插信号注入延迟级的输入。中央插值器提供精细的相位控制。此外，可以通过选择性地将内插信号注入到给定的延迟级中来可选地实现粗略的相位控制。公开了使用多个内插器的粗略和精细相位控制的另一个电压控制延迟回路。

2. 发明申请

US20070052460A1 Statically controlled clock source generator for VCDL clock phase trimming 失效
公开(公告)号：US20070052460A1
公开(公告)日：2007-03-08
申请号：US11221316
申请日：2005-09-07
申请人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
发明人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H04L7/0337
摘要： The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.

3. 发明申请

US20060268958A1 Methods and apparatus for spread spectrum generation using a voltage controlled delay loop 有权
标题翻译：使用电压控制延迟环路进行扩频生成的方法和装置
公开(公告)号：US20060268958A1
公开(公告)日：2006-11-30
申请号：US11141695
申请日：2005-05-31
申请人： Vladimir Sindalovsky , Lane Smith , Craig Ziemer
发明人： Vladimir Sindalovsky , Lane Smith , Craig Ziemer
IPC分类号： H04B1/00
CPC分类号： H04B15/02 , H04B2215/067
摘要： Methods and apparatus are provided for generating a frequency with a predefined offset from a reference frequency. A spread spectrum generator circuit is disclosed that comprises a voltage controlled delay loop for generating a plurality of signals having a different phase; and at least one interpolator for processing at least two of the signals to generate an output signal having a phase between a phase of the at least two of the signals, wherein the output is varied between a phase of the at least two of the signals to generate the spread spectrum. A spread spectrum having a frequency lower than an applied clock signal is generated using a continuous phase delay increase and a spread spectrum having a frequency higher than the clock signal is generated using a continuous phase delay decrease.
摘要翻译：提供了用于产生具有与参考频率的预定义偏移的频率的方法和装置。公开了一种扩频发生器电路，其包括用于产生具有不同相位的多个信号的电压控制延迟环路; 以及至少一个内插器，用于处理至少两个所述信号以产生具有所述至少两个所述信号的相位之间的相位的输出信号，其中所述输出在所述至少两个信号的相位之间变化生成扩频。使用连续的相位延迟增加来产生频率低于所施加的时钟信号的扩展频谱，并且使用连续的相位延迟减小产生具有高于时钟信号的频率的扩频。

4. 发明申请

US20070217558A1 Method and apparatus for improving linearity in clock and data recovery systems 有权
标题翻译：提高时钟和数据恢复系统线性度的方法和装置
公开(公告)号：US20070217558A1
公开(公告)日：2007-09-20
申请号：US11375828
申请日：2006-03-15
申请人： Christopher Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig Ziemer
发明人： Christopher Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig Ziemer
IPC分类号： H04L7/00
CPC分类号： H04L7/0008
摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. A data stream is received and the phase of a clock signal is adjusted using two interpolators. The data stream is then recovered using the clock signal.
摘要翻译：公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。接收数据流，并使用两个内插器调整时钟信号的相位。然后使用时钟信号恢复数据流。

5. 发明申请

US20070189360A1 Method and apparatus for generation of asynchronous clock for spread spectrum transmission 有权
标题翻译：用于产生扩频传输的异步时钟的方法和装置
公开(公告)号：US20070189360A1
公开(公告)日：2007-08-16
申请号：US11353431
申请日：2006-02-14
申请人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , William Wilson , Craig Ziemer
发明人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , William Wilson , Craig Ziemer
IPC分类号： H03D3/24 , H03D1/00 , H03D3/18 , H04L27/06 , H04B1/00
CPC分类号： H04L27/0014 , H04B1/7075 , H04L2027/0036
摘要： A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a third signal and a fourth signal and generate a second output signal based on a second control signal. A multiplexer is used to select, based on a select signal, the first output signal or the second output signal as a spread spectrum clock (SSCLK). A leap-frog interpolator control is used to generate, in synchronism with the SSCLK, the first control signal based on a first type of phase adjustment request, the second control signal based on a second type of phase adjustment request, and the select signal to switch the multiplexer between the first output signal and the second output signal after allowing for an interpolator settling time when changing the first control signal or the second control signal.
摘要翻译：用于扩频率控制的电路使用第一内插器在第一信号和第二信号之间进行相位插值，并且基于第一控制信号产生第一输出信号。第二内插器用于在第三信号和第四信号之间进行相位插值，并且基于第二控制信号产生第二输出信号。多路复用器用于基于选择信号选择第一输出信号或第二输出信号作为扩频时钟（SSCLK）。跳跃内插器控制用于与SSCLK同步地产生基于第一类型的相位调整请求的第一控制信号，基于第二类型的相位调整请求的第二控制信号，以及选择信号在改变第一控制信号或第二控制信号之后允许内插器稳定时间之后，在第一输出信号和第二输出信号之间切换多路复用器。

6. 发明申请

US20060267660A1 Alternating clock signal generation for delay loops 失效
标题翻译：用于延迟环的交替时钟信号生成
公开(公告)号：US20060267660A1
公开(公告)日：2006-11-30
申请号：US11138777
申请日：2005-05-26
申请人： Christopher Abel , Vladimir Sindalovsky , Craig Ziemer
发明人： Christopher Abel , Vladimir Sindalovsky , Craig Ziemer
IPC分类号： G06F1/04
CPC分类号： H04L7/0025 , H03L7/07 , H03L7/0814 , H04L7/0337
摘要： A delay loop (e.g., a voltage-controlled delay loop) has (at least) two devices (e.g., interpolators) for generating clock signals for injection into the delay elements of the delay loop in a leap-frog manner, in which, while one interpolator is generating the clock signal currently selected for injection, the other interpolator can be controlled to generate the next clock signal to be selected for injection. This leap-frog technique can provide more settling time for generating injected clock signals than implementations that rely on a single interpolator.
摘要翻译：延迟环路（例如，电压控制延迟环路）具有（至少）两个用于产生用于以跳跃方式注入到延迟环路的延迟元件中的时钟信号的器件（例如，内插器），其中，一个内插器正在产生当前被选择用于注入的时钟信号，另一个内插器可被控制以产生要被选择用于注入的下一个时钟信号。这种跳跃式技术可以提供更多的建立时间来产生注入的时钟信号，而不是依赖于单个内插器的实现。

7. 发明授权

US08385493B2 Method and apparatus for improving linearity in clock and data recovery systems 有权
标题翻译：提高时钟和数据恢复系统线性度的方法和装置
公开(公告)号：US08385493B2
公开(公告)日：2013-02-26
申请号：US12755522
申请日：2010-04-07
申请人： Christopher Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig Ziemer
发明人： Christopher Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig Ziemer
IPC分类号： H04L7/02
CPC分类号： H04L7/0008
摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.
摘要翻译：公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被非激活。当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。然后使用延迟环路的输出作为时钟信号来恢复数据流。

8. 发明申请

US20100195777A1 METHOD AND APPARATUS FOR IMPROVING LINEARITY IN CLOCK AND DATA RECOVERY SYSTEMS 有权
标题翻译：用于改进时钟和数据恢复系统中的线性的方法和装置
公开(公告)号：US20100195777A1
公开(公告)日：2010-08-05
申请号：US12755522
申请日：2010-04-07
申请人： Christopher Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig Ziemer
发明人： Christopher Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig Ziemer
IPC分类号： H04L7/033
CPC分类号： H04L7/0008
摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.
摘要翻译：公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被去激活。当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。然后使用延迟环路的输出作为时钟信号来恢复数据流。

9. 发明授权

US07724857B2 Method and apparatus for improving linearity in clock and data recovery systems 有权
标题翻译：提高时钟和数据恢复系统线性度的方法和装置
公开(公告)号：US07724857B2
公开(公告)日：2010-05-25
申请号：US11375828
申请日：2006-03-15
申请人： Christopher Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig Ziemer
发明人： Christopher Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig Ziemer
IPC分类号： H04L7/00
CPC分类号： H04L7/0008
摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.
摘要翻译：公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被非激活。当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。然后使用延迟环路的输出作为时钟信号来恢复数据流。

10. 发明申请

US20090175395A1 DATA ALIGNMENT METHOD FOR ARBITRARY INPUT WITH PROGRAMMABLE CONTENT DESKEWING INFO 有权
标题翻译：具有可编程内容描述信息的仲裁输入的数据对齐方法
公开(公告)号：US20090175395A1
公开(公告)日：2009-07-09
申请号：US11969440
申请日：2008-01-04
申请人： Yasser AHMED , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
发明人： Yasser AHMED , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
IPC分类号： H04L7/00
CPC分类号： H03M9/00 , H04L7/005 , H04L7/04
摘要： In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.
摘要翻译：在示例性实施例中，数据对准系统包括先进先出寄存器（FIFO），连接到FIFO的可编程模式发生器和连接到可编程模式发生器和FIFO的控制器。 FIFO被配置为向具有一个或多个通道的串行数据链路的第一数据通道提供数据或从其接收数据。串行数据链路的每个数据通道被配置为发送相应的串行数据流。可编程模式发生器被配置为生成多个对准符号。控制器被配置为管理串行数据链路的一个或多个数据通道的对准以及将多个对准符号中选择的一个对准符号插入到每个串行数据流中。

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