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31. 发明授权

US5728599A Printable superconductive leadframes for semiconductor device assembly 失效
标题翻译：用于半导体器件组装的可印刷超导引线框架
公开(公告)号：US5728599A
公开(公告)日：1998-03-17
申请号：US432539
申请日：1995-08-07
申请人： Michael D. Rostoker , Mark Schneider , Chok J. Chia
发明人： Michael D. Rostoker , Mark Schneider , Chok J. Chia
IPC分类号： H01L21/48 , H01L23/495 , H01L21/283 , H01L21/58 , H01L21/60
CPC分类号： H01L24/50 , H01L21/4821 , H01L23/49579 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01056 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , Y10S505/703 , Y10S505/706 , Y10S505/741 , Y10T29/49121
摘要： Process for manufacturing a high interconnection density, fine-line, superconductive printed leadframes using thick-film screen-printing techniques, or other printing techniques. Generally, a superconductive leadframe pattern is printed on a backing substrate. Once the pattern is cured, the backing substrate, or portions thereof can be removed. The backing substrate can be a "fish paper" substrate treated with a release agent, or other substrate material which can be dissolved away, etched away, or otherwise removed. Portions of the backing substrate can be used to provide mechanical integrity for the leadframe. The leadframe fingers can be printed using a superconductive paste or a superconductive precursor paste which is subsequently treated to exhibit superconductivity.
摘要翻译：使用厚膜丝网印刷技术制造高互连密度，细线，超导印刷引线框的方法或其它印刷技术。通常，超导引线框架图案印刷在背衬基板上。一旦图案固化，背衬基底或其部分可以被去除。背衬基材可以是用脱模剂处理的“鱼纸”基材，或可以溶解掉，蚀刻掉或以其它方式除去的其它基材。背衬基板的一部分可用于为引线框架提供机械完整性。引线框指可以使用超导糊或超导前体糊进行印刷，其随后被处理以显示超导性。

32. 发明授权

US5568683A Method of cooling a packaged electronic device 失效
标题翻译：冷却电子装置的方法
公开(公告)号：US5568683A
公开(公告)日：1996-10-29
申请号：US472320
申请日：1995-06-07
申请人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
发明人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
IPC分类号： F02F7/00 , H01L23/367 , H01L23/40 , H05K3/30
CPC分类号： H01L23/40 , F02F7/00 , H01L23/3675 , H01L2924/0002 , Y10T29/4913
摘要： A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.
摘要翻译：提供了由散热器单元和散热器组成的可拆卸的散热器组件。散热器单元具有至少一个翅片和用于从封装的电子设备辐射热量的联接套环。散热器包括附接到与封装的电子设备热接触的内部套环的平台。该平台具有一个或多个适合于与位于散热器单元的联接环上的一个或多个凸缘相配合的凸片。当凸缘与散热片接头配合并且散热片转动时，凸缘内的耦合凹槽接合散热器的平台。因此，散热器可以快速方便地附接到散热器或从散热器移除。因此，本发明允许各种不同的散热器与附接到电子设备封装的单个散热器可互换地使用。

33. 发明授权

US5185653A O-ring package 失效
标题翻译： O型圈包装
公开(公告)号：US5185653A
公开(公告)日：1993-02-09
申请号：US661962
申请日：1991-02-28
申请人： Andrew P. Switky , Chok J. Chia
发明人： Andrew P. Switky , Chok J. Chia
IPC分类号： H01L21/50 , H01L23/057 , H01L23/16 , H01L23/495
CPC分类号： H01L21/50 , H01L23/057 , H01L23/16 , H01L23/49558 , H01L2224/45124 , H01L2224/48091 , H01L2224/48247 , H01L24/45 , H01L24/48 , H01L2924/12042 , H01L2924/14 , H01L2924/15747
摘要： A transfer molded plastic package having a cavity for accommodating a semiconductor chip is disclosed. A leadframe assembly process is shown wherein the leadframe finger pattern is provided with a resilient or elastic O-ring bead. Top and bottom housing plates which have dimensions that are larger than the bead form the upper and lower surfaces of the package. These plates can be formed of any suitably rigid material. They may be composed of ceramic in low power devices. For high power operation at least one metal plate can be employed. The chip or chips are connected to the lead frame and, along with the top and bottom plates, is located in a transfer mold. The plates are in registy and located so that their outer edges extend beyond the O-ring bead. The mold cavities include faces which press against the plates which are held apart by the O-ring bead so that the bead is compressed by the mold closure. A plastic encapsulant is molded around the periphery of the plates so that the leadframe fingers are secured therein to become package pins.
摘要翻译：公开了一种具有用于容纳半导体芯片的空腔的转移模制塑料封装。示出了引线框架组装过程，其中引线框指状图案设置有弹性或弹性O形环珠。具有大于珠的尺寸的顶部和底部壳体板形成包装的上表面和下表面。这些板可以由任何适当刚性的材料形成。它们可以由低功率器件中的陶瓷组成。对于大功率操作，可以使用至少一个金属板。芯片或芯片连接到引线框架，并且与顶板和底板一起位于转移模具中。板被配准并且定位成使得它们的外边缘延伸超过O形圈珠。模具腔包括压靠在板上的面，这些面被O形圈珠保持分开，使得胎圈被模具盖压缩。围绕板的周边模塑塑料密封剂，使得引线框架指状物固定在其中以成为封装销。

34. 发明授权

US4688152A Molded pin grid array package GPT 失效
标题翻译：模压针阵列封装GPT
公开(公告)号：US4688152A
公开(公告)日：1987-08-18
申请号：US895395
申请日：1986-08-11
申请人： Chok J. Chia
发明人： Chok J. Chia
IPC分类号： H01L23/498 , H05K7/06
CPC分类号： H01L23/49827 , H01L2224/48091 , Y10T29/49146
摘要： A pin-grid package is created by starting with printed wiring boards that have plated through holes that can accommodate wire pins. Pins are secured in position to extend outward from one face of the PW board in the form of a pin grid array of the desired configuration which is typically a plurality of concentric rings thereby creating a square grid pattern of predetermined spacing. The opposing PW board face includes a central pin-free area to which is secured a semiconductor die. This face of the PW board includes a plurality of wiring traces that connect each pin to an array that surrounds the semiconductor die. The traces are connected to the bonding pads of the semiconductor die by either wire bonds or a spider assembly using tape assembly bonding. The PW board is located in a mold that has a flat faced first platen that contains cut-out regions that will accommodate the package pins. The other flat-faced mold platen contains molding cavities that are in registry with and slightly larger than the PW boards. The mold cavities include a series of ribs that are distributed around the cavity periphery. These ribs bear against the PW board when the mold is assembled so that the PW board is centered and pressed against the flat face of first platen in the region outboard of the pin-grid pattern. When a liquified plastic encapsulant is forced into the mold the cavities will be filled and the liquid will be excluded from the pin side of the PW board.
摘要翻译：通过从具有电镀通孔的印刷电路板开始，可以容纳线引脚，从而创建一个针格栅封装。引脚被固定就位，从PW板的一个面向外延伸，形式为通常是多个同心环的所需结构的销栅格阵列形式，从而产生预定间隔的正方形网格图案。相对的PW板面包括固定半导体管芯的中心无引脚区域。 PW板的该面包括将每个引脚连接到围绕半导体管芯的阵列的多个布线迹线。迹线通过线接合或者使用带组件接合的蜘蛛组件连接到半导体管芯的接合焊盘。 PW板位于模具中，该模具具有平坦的第一压板，其包含将容纳封装销的切口区域。另一个平面模具压板包含与PW板对准并略大的模制腔。模腔包括分布在腔周边周围的一系列肋。当模具组装时，这些肋承载在PW板上，使得PW板在针脚格栅图案外侧的区域中心并压靠在第一压板的平面上。当液态塑料密封剂被迫进入模具时，空腔将被填充，并且液体将从PW板的销侧排除。

35. 发明授权

US07804167B2 Wire bond integrated circuit package for high speed I/O 有权
标题翻译： Wire Bond集成电路封装，适用于高速I / O
公开(公告)号：US07804167B2
公开(公告)日：2010-09-28
申请号：US11565701
申请日：2006-12-01
申请人： Clifford Fishley , Abiola Awujoola , Leonard Mora , Amar Amin , Maurice Othieno , Chok J. Chia
发明人： Clifford Fishley , Abiola Awujoola , Leonard Mora , Amar Amin , Maurice Othieno , Chok J. Chia
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L23/66 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L2224/451 , H01L2224/45147 , H01L2224/48233 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00015 , H01L2224/05599
摘要： An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
摘要翻译：一种集成电路封装，包括封装基板，形成在封装基板上的管芯安装焊盘，用于将管芯固定到封装基板;形成在封装基板上的接地环，用于将芯和I / O接地线连接在管芯和管芯之间; 所述封装基板和紧邻所述接地环形成的第一多个接合指，用于在所述封装基板和所述管芯之间附接第一组I / O信号接合线。

36. 发明申请

US20100067207A1 SEMICONDUCTOR PACKAGE AND METHOD USING ISOLATED VSS PLANE TO ACCOMMADATE HIGH SPEED CIRCUITRY GROUND ISOLATION 有权
标题翻译：半导体封装和使用隔离的VSS平面到接地高速电路分离的方法
公开(公告)号：US20100067207A1
公开(公告)日：2010-03-18
申请号：US12625457
申请日：2009-11-24
申请人： Maurice O. Othieno , Chok J. Chia , Amar J. Amin
发明人： Maurice O. Othieno , Chok J. Chia , Amar J. Amin
IPC分类号： H01R9/00 , H01L23/48
CPC分类号： H01L23/50 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/48091 , H01L2224/4943 , H01L2225/06562 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
摘要翻译：本发明的实施例包括半导体集成电路封装，其包括可以具有附接到其上的集成电路管芯的衬底。该封装包括与用于接地封装的低速电路的地平面电隔离的专用高速接地层。

37. 发明申请

US20080128919A1 WIRE BOND INTEGRATED CIRCUIT PACKAGE FOR HIGH SPEED I/O 有权
标题翻译：用于高速I / O的线束集成电路封装
公开(公告)号：US20080128919A1
公开(公告)日：2008-06-05
申请号：US11565701
申请日：2006-12-01
申请人： Clifford Fishley , Abiola Awujoola , Leonard Mora , Amar Amin , Maurice Othieno , Chok J. Chia
发明人： Clifford Fishley , Abiola Awujoola , Leonard Mora , Amar Amin , Maurice Othieno , Chok J. Chia
IPC分类号： H01L23/49 , H01L21/44
CPC分类号： H01L23/66 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L2224/451 , H01L2224/45147 , H01L2224/48233 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00015 , H01L2224/05599
摘要： An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
摘要翻译：一种集成电路封装，包括封装基板，形成在封装基板上的管芯安装焊盘，用于将管芯固定到封装基板;形成在封装基板上的接地环，用于将芯和I / O接地线连接在管芯和管芯之间; 所述封装衬底以及紧邻所述接地环形成的第一多个接合指，用于在所述封装衬底和所述管芯之间附接第一组I / O信号接合线。

38. 发明授权

US06991147B2 Insulated bonding wire tool for microelectronic packaging 失效
标题翻译：用于微电子封装的绝缘接合线工具
公开(公告)号：US06991147B2
公开(公告)日：2006-01-31
申请号：US10642706
申请日：2003-08-18
申请人： Chok J. Chia , Owai H. Low , Ramaswamy Ranganathan
发明人： Chok J. Chia , Owai H. Low , Ramaswamy Ranganathan
IPC分类号： B23K31/02 , B05D5/12
CPC分类号： H01L24/85 , H01L23/4952 , H01L24/45 , H01L24/48 , H01L24/78 , H01L2224/05554 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/78301 , H01L2224/8502 , H01L2224/85181 , H01L2224/8592 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01079 , H01L2924/20753 , H01L2924/06 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.
摘要翻译：一种用于绝缘接合线的方法，包括以下步骤：将接合线附接到接合焊盘，并且用绝缘液体涂覆接合线，同时将接合线通过接合工具从接合焊盘牵引到封装引线。

39. 发明授权

US06285077B1 Multiple layer tape ball grid array package 有权
标题翻译：多层磁带球栅阵列封装
公开(公告)号：US06285077B1
公开(公告)日：2001-09-04
申请号：US09377887
申请日：1999-08-19
申请人： Chok J. Chia , Seng-Sooi Allen Lim , Qwai Hoong Low
发明人： Chok J. Chia , Seng-Sooi Allen Lim , Qwai Hoong Low
IPC分类号： H01L2348
CPC分类号： H01L23/3128 , H01L23/49833 , H01L24/48 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A package for an integrated circuit is disclosed. The package comprises two layers (a top layer and a bottom layer) of flexible tape, each of which has a top surface and a bottom surface, with metal traces on the top surface. A die is mounted on top of the two layers and wire bonds connect bond pads on the die to metal traces on each of the two flexible tapes. The metal traces are routed along the top surfaces of the flexible tapes and are coupled to solder balls through holes in the tapes. These solder balls are mounted along the bottom of the package and serve as the electrical interface to a printed circuit board. Additional holes in the bottom layer tape allow solder balls to extend through the bottom layer tape so that they may be electrically coupled to traces on the top layer tape.
摘要翻译：公开了一种用于集成电路的封装。该包装包括柔性带的两层（顶层和底层），每层具有顶表面和底表面，顶表面具有金属迹线。模具安装在两层的顶部，引线接合将模具上的接合焊盘连接到两个柔性带中的每一个上的金属迹线。金属迹线沿着柔性带的顶表面布线，并通过带中的孔耦合到焊球。这些焊球沿着封装的底部安装并用作印刷电路板的电接口。底层带中的另外的孔允许焊球延伸穿过底层带，使得它们可以电耦合到顶层带上的迹线。

40. 发明授权

US5521427A Printed wiring board mounted semiconductor device having leadframe with alignment feature 失效
标题翻译：印刷线路板安装的半导体器件具有引导框架，具有对准特征
公开(公告)号：US5521427A
公开(公告)日：1996-05-28
申请号：US340807
申请日：1994-11-17
申请人： Chok J. Chia , Seng-Sooi Lim
发明人： Chok J. Chia , Seng-Sooi Lim
IPC分类号： H01L23/495 , H05K3/30 , H05K3/34 , H01L23/544
CPC分类号： H05K3/303 , H01L23/49541 , H01L2224/48091 , H01L2224/48247 , H05K2201/10303 , H05K2201/10659 , H05K2201/10689 , H05K2201/10962 , H05K2203/167 , H05K3/3421 , Y02P70/613 , Y10S438/975 , Y10T29/49121 , Y10T29/49133
摘要： A packaged semiconductor device, leadframe for making same, and method of mounting same to a printed circuit board are described. The device has a body, and a plurality of leads extending from the body. One or more alignment features are formed on the exterior of the package body, for maintaining precise alignment of the device with respect to a printed wiring board. The alignment feature is a tab formed as part of portion of the leadframe external to the package body. The tab may have various shapes, and may be provided with a hole for registering with a pin on an underlying substrate, such as a printed wiring board. The pin and the tab may be electrically connected.
摘要翻译：描述了一种封装的半导体器件，用于制造其的引线框，以及将其安装到印刷电路板的方法。该装置具有主体和从主体延伸的多个引线。一个或多个对准特征形成在包装体的外部上，以保持装置相对于印刷线路板的精确对准。对准特征是形成为包装体外部的引线框架的一部分的突片。突片可以具有各种形状，并且可以设置有用于与诸如印刷线路板的下面的基板上的销对准的孔。引脚和突片可以电连接。

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