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31. 发明授权

US06528855B2 MOSFET having a low aspect ratio between the gate and the source/drain 失效
标题翻译： MOSFET在栅极和源极/漏极之间具有低的纵横比
公开(公告)号：US06528855B2
公开(公告)日：2003-03-04
申请号：US09911894
申请日：2001-07-24
申请人： Qiuyi Ye , William Tonti , Yujun Li , Jack A. Mandelman
发明人： Qiuyi Ye , William Tonti , Yujun Li , Jack A. Mandelman
IPC分类号： H01L29772
CPC分类号： H01L29/0653 , H01L21/823814 , H01L21/823878 , H01L29/66621 , H01L29/66636 , H01L29/7834
摘要： A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.
摘要翻译：具有新的源极/漏极（S / D）结构的MOSFET特别适用于现代CMOS技术的较小特征尺寸。 S / D导体位于浅沟槽隔离（STI）上，以实现低结漏电和低结电容。通过STI蚀刻步骤（根据制造MOSFET的第一种方法）或硅蚀刻步骤（根据制造MOSFET的第二种方法）限定S / D结深度。通过控制蚀刻深度，实现非常浅的结深度。栅极长度的变化很小，因为栅极区域是通过蚀刻晶体硅来定义的，而不是蚀刻多晶硅。由于栅极导体和源极和漏极导体在同一个电平上对齐，栅极和S / D之间的纵横比较低。自杀技术应用于源极和漏极，用于低寄生电阻; 然而，这不会导致严重的S / D结泄漏，因为源极和漏极导体位于STI上。

32. 发明申请

US20090302416A1 Programmable Electrical Fuse 有权
标题翻译：可编程电气保险丝
公开(公告)号：US20090302416A1
公开(公告)日：2009-12-10
申请号：US12135242
申请日：2008-06-09
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
摘要翻译：本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

33. 发明申请

US20090212362A1 SOI FIELD EFFECT TRANSISTOR WITH A BACK GATE FOR MODULATING A FLOATING BODY 失效
标题翻译：具有用于调制浮动体的后盖的SOI场效应晶体管
公开(公告)号：US20090212362A1
公开(公告)日：2009-08-27
申请号：US12036325
申请日：2008-02-25
申请人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
发明人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
IPC分类号： H01L21/84 , H01L29/786
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66772 , H01L29/78612 , H01L29/78648
摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.
摘要翻译：将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。

34. 发明申请

US20080057671A1 SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION AND METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES 有权
标题翻译：用于锁定抑制的半导体结构和形成这种半导体结构的方法
公开(公告)号：US20080057671A1
公开(公告)日：2008-03-06
申请号：US11927135
申请日：2007-10-29
申请人： Toshiharu Furukawa , Robert Gauthier , David Horak , Charles Koburger , Jack Mandelman , William Tonti
发明人： Toshiharu Furukawa , Robert Gauthier , David Horak , Charles Koburger , Jack Mandelman , William Tonti
IPC分类号： H01L21/762
CPC分类号： H01L21/76237 , H01L21/26533 , H01L21/76213 , H01L21/76229 , H01L21/76232 , H01L21/823878 , H01L27/0921 , H01L29/1087 , H01L29/78
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。该半导体结构包括成形修饰的隔离区，其形成在通常在制造本体CMOS器件的衬底的两个掺杂阱之间的沟槽中。成形改进的隔离区域可以包括沟槽的加宽的电介质填充部分，其可以可选地包括分隔两个掺杂阱之间的损伤区域的沟槽的附近损伤区域或狭窄的电介质填充部分。也可以通过在沟槽中的沟槽基底和介电填料之间提供晶格不匹配的层来抑制闩锁。

35. 发明申请

US20080048265A1 SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES 有权
公开(公告)号：US20080048265A1
公开(公告)日：2008-02-28
申请号：US11927110
申请日：2007-10-29
申请人： Roger Booth , Jack Mandelman , William Tonti
发明人： Roger Booth , Jack Mandelman , William Tonti
IPC分类号： H01L27/12
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/82385 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

36. 发明申请

US20070298526A1 PROGRAMMABLE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：可编程半导体器件
公开(公告)号：US20070298526A1
公开(公告)日：2007-12-27
申请号：US11768208
申请日：2007-06-26
申请人： Wayne Berry , John Fifield , William Guthrie , Richard Kontra , William Tonti
发明人： Wayne Berry , John Fifield , William Guthrie , Richard Kontra , William Tonti
IPC分类号： G01R31/26
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A design structure for designing and manufacturing a programmable device. The design structure includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译：用于设计和制造可编程器件的设计结构。设计结构包括基板（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）基本上比第二端部（12b）更宽，并且金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。

37. 发明申请

US20070210412A1 ELECTRICALLY PROGRAMMABLE PI-SHAPED FUSE STRUCTURES AND METHODS OF FABRICATION THEREOF 有权
标题翻译：电气可编程PI形状的保险丝结构及其制造方法
公开(公告)号：US20070210412A1
公开(公告)日：2007-09-13
申请号：US11372380
申请日：2006-03-09
申请人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
发明人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.
摘要翻译：提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙上方，在一个实施例中，熔断元件由围绕熔丝元件的绝热介电材料覆盖。

38. 发明申请

US20070182030A1 High-voltage silicon-on-insulator transistors and methods of manufacturing the same 失效
标题翻译：高压硅绝缘体晶体管及其制造方法
公开(公告)号：US20070182030A1
公开(公告)日：2007-08-09
申请号：US11347413
申请日：2006-02-03
申请人： William Ma , Jack Mandelman , Carl Radens , William Tonti
发明人： William Ma , Jack Mandelman , Carl Radens , William Tonti
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/66772 , H01L29/78612 , H01L29/78624 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了制造高压晶体管的第一种方法。第一种方法包括以下步骤：（1）提供包括在绝缘体上硅（SOI）层之下的绝缘体层下面的体硅层的衬底; 以及（2）形成包括SOI层中的晶体管的扩散区域的晶体管节点的一个或多个部分。晶体管节点的一部分适于将晶体管内的大于约5V的电压减小到小于约3V的电压。提供了许多其它方面。

39. 发明申请

US20070173029A1 Method for fabricating high performance metal-insulator-metal capacitor (MIMCAP) 审中-公开
标题翻译：制造高性能金属绝缘体金属电容器（MIMCAP）的方法
公开(公告)号：US20070173029A1
公开(公告)日：2007-07-26
申请号：US11340340
申请日：2006-01-26
申请人： Wagdi Abadeer , Jack Mandelman , Carl Radens , William Tonti
发明人： Wagdi Abadeer , Jack Mandelman , Carl Radens , William Tonti
IPC分类号： H01L21/20
CPC分类号： H01L28/60
摘要： A method of fabricating a high performance metal-insulator-metal capacitor (MIMCAP) includes providing a first inter-level dielectric (ILD) layer over an isolation region; forming a MIMCAP pattern in the first ILD layer over the isolation region; depositing a conformal conductive liner over the MIMCAP pattern and the first ILD layer; depositing an insulator over the conformal conductive liner; forming a contact pattern through the conformal conductive liner, the insulator and the first inter-level dielectric (ILD) layer; depositing a second conformal conductive liner over the MIMCAP pattern, the contact pattern and the first ILD layer; and depositing a conductive stud over the second conformal conductive liner in the MIMCAP pattern and the contact pattern. The method is applicable to both a conventional bulk semiconductor substrate and a silicon-on-insulator (SOI) substrate.
摘要翻译：一种制造高性能金属 - 绝缘体 - 金属电容器（MIMCAP）的方法包括在隔离区域上提供第一级间电介质层（ILD）层; 在隔离区域上的第一ILD层中形成MIMCAP图案; 在MIMCAP图案和第一ILD层上沉积共形导电衬垫; 在保形导电衬垫上沉积绝缘体; 通过所述共形导电衬垫，所述绝缘体和所述第一层间电介质层（ILD）层形成接触图案; 在MIMCAP图案，接触图案和第一ILD层上沉积第二共形导电衬垫; 以及在MIMCAP图案和接触图案中的第二共形导电衬垫上沉积导电柱。该方法适用于常规体半导体衬底和绝缘体上硅（SOI）衬底。

40. 发明申请

US20070170521A1 METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING 有权
公开(公告)号：US20070170521A1
公开(公告)日：2007-07-26
申请号：US11306827
申请日：2006-01-12
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211
摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

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