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31. 发明申请

US20090140440A1 MULTI-CHIP STACK STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：多芯片堆叠结构及其制作方法
公开(公告)号：US20090140440A1
公开(公告)日：2009-06-04
申请号：US12266830
申请日：2008-11-07
申请人： Chung-Lun Liu , Jung-Pin Huang , Yi-Feng Chang , Chin-Huang Chang
发明人： Chung-Lun Liu , Jung-Pin Huang , Yi-Feng Chang , Chin-Huang Chang
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L25/50 , H01L21/56 , H01L23/3107 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L25/0657 , H01L25/18 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83 , H01L2224/858 , H01L2224/8592 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/15313 , H01L2924/15321 , H01L2924/15323 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficulty.
摘要翻译：提供了一种多芯片堆叠结构及其制造方法。制造多芯片堆叠结构的方法包括通过使用阶梯状方式将包括多个第一芯片的第一芯片组布置在芯片载体上，将第二芯片设置在第一芯片组的顶部上的第一芯片上，通过接合线将第一芯片组和第二芯片电连接到芯片载体上，使用薄膜覆盖线（FOW）来在第一芯片和第二芯片之间设置绝缘膜，其中绝缘膜覆盖部分在第一组的顶部和第二芯片的至少一部分上的第一芯片的接合线的端部，并且通过接合线将第三芯片电连接到芯片载体，从而防止直接布置在第一芯片上第二芯片的平面尺寸远远小于现有技术中的第一芯片的平面尺寸，这增加了整个结构的高度并增加了布线粘合难度。

32. 发明申请

US20080303134A1 Semiconductor package and method for fabricating the same 审中-公开
标题翻译：半导体封装及其制造方法
公开(公告)号：US20080303134A1
公开(公告)日：2008-12-11
申请号：US12156875
申请日：2008-06-05
申请人： Chun-Yuan Li , Hsiao-Jen Hung , Chin-Huang Chang , Jeng-Yuan Lai
发明人： Chun-Yuan Li , Hsiao-Jen Hung , Chin-Huang Chang , Jeng-Yuan Lai
IPC分类号： H01L23/52 , H01L21/02
CPC分类号： H01L21/4832 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L23/49582 , H01L24/27 , H01L24/48 , H01L2224/48091 , H01L2224/73265 , H01L2224/85001 , H01L2224/85444 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H05K3/341 , H05K3/3436 , H05K2201/0373 , H05K2201/09472 , H05K2201/10727 , H05K2201/10969 , Y02P70/613 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a method for fabricating the same are disclosed, which includes: providing a carrier board, forming a plurality of metal bumps on the carrier board, forming a metal layer on the carrier board to encapsulate the metal bumps, having at least one semiconductor chip electrically connected to the metal layer, then forming an encapsulant on the carrier board to encapsulate the semiconductor chip, and next removing the carrier board and the metal bumps to correspondingly form a plurality of grooves on surface of the encapsulant, wherein bottom and sides of the grooves are covered with the metal layer to allow electroconductive components to be effectively positioned in the grooves and completely bonded with the metal layer.
摘要翻译：公开了一种半导体封装及其制造方法，其包括：提供载体板，在载体板上形成多个金属凸块，在载体板上形成金属层以封装金属凸块，具有至少一个半导体芯片与金属层电连接，然后在载体板上形成密封剂以封装半导体芯片，接着去除载体板和金属凸块，以在密封剂的表面上相应地形成多个凹槽，其中底部和侧面的沟槽被金属层覆盖以允许导电部件有效地定位在槽中并与金属层完全粘合。

33. 发明申请

US20070108571A1 Method for fabricating semiconductor package with stacked chips 有权
标题翻译：制造具有堆叠芯片的半导体封装的方法
公开(公告)号：US20070108571A1
公开(公告)日：2007-05-17
申请号：US11649144
申请日：2007-01-02
申请人： Jung-Pin Huang , Chin-Huang Chang , Chung-Lun Liu
发明人： Jung-Pin Huang , Chin-Huang Chang , Chung-Lun Liu
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49575 , H01L23/3135 , H01L23/49531 , H01L24/48 , H01L24/49 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/4911 , H01L2924/00014 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.
摘要翻译：提出了一种具有堆叠芯片的半导体封装及其制造方法。半导体封装包括具有多个引线和支撑延伸部的引线框架; 至少一个具有活性表面的预制包装和连接到引线框架的支撑延伸部的非活性表面; 至少一个芯片安装在所述预制包装的有效表面上; 用于将引线框架，预成型封装和芯片电连接的多个接合线; 以及用于封装预制包装，芯片，接合线和引线框架的一部分的密封剂。预制包装的活性表面用于承载芯片，并且可以用作跳线，以便解决多芯片模块的已知的良好的裸片（KGD）问题。

34. 发明申请

US20060071220A1 Semiconductor package including light emitter and IC 有权
标题翻译：半导体封装包括发光器和IC
公开(公告)号：US20060071220A1
公开(公告)日：2006-04-06
申请号：US11237137
申请日：2005-09-28
申请人： Wei Lung Lu , Cheng Jen Liu , Chin-Huang Chang , Yi-Feng Chang
发明人： Wei Lung Lu , Cheng Jen Liu , Chin-Huang Chang , Yi-Feng Chang
IPC分类号： H01L31/12
CPC分类号： H01L25/167 , H01L2224/48091 , H01L2224/48227 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00014 , H01L2924/00012
摘要： The is to disclose a semiconductor package featuring inclusion of light emitter(s) providing light to indicate the states of the semiconductor package as a whole and/or the chip(s) therein. The light emitter is in an original state or flashing state or emitting state according to the states of the semiconductor package as a whole and/or the chip(s). The semiconductor package includes a carrier and a shield structure in addition to the light emitter. The chip and at least part of the carrier are covered by the shield structure. The light emitter may be partially or fully covered or sealed by the shield structure. The light emitter may also be partially or fully exposed. The shield structure is such that the light provided by the light emitter sealed therein can pass therethrough to reach the outside thereof, thereby the states of the semiconductor package as a whole and/or the chip(s) can be recognized from the outside of the semiconductor package.
摘要翻译：公开了一种包括提供光的发光体的半导体封装，以指示半导体封装作为整体的状态和/或其中的芯片。根据半导体封装整体的状态和/或芯片，光发射器处于原始状态或闪烁状态或发光状态。除了发光体之外，半导体封装还包括载体和屏蔽结构。芯片和载体的至少一部分被屏蔽结构覆盖。光发射器可以被屏蔽结构部分地或完全地覆盖或密封。光发射器也可以部分地或完全暴露。屏蔽结构使得由其中密封的发光器提供的光可以通过其中以到达其外部，从而可以从外部识别半导体封装的整体状态和/或芯片半导体封装。

35. 发明授权

US06835897B2 Warpage preventing substrate 有权
公开(公告)号：US06835897B2
公开(公告)日：2004-12-28
申请号：US10309564
申请日：2002-12-04
申请人： Chin-Huang Chang , Chin-Tien Chiu , Cheng-Lun Liu
发明人： Chin-Huang Chang , Chin-Tien Chiu , Cheng-Lun Liu
IPC分类号： H05K103
CPC分类号： H01L23/145 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/49894 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48227 , H01L2224/48228 , H01L2924/00014 , H01L2924/01079 , H01L2924/181 , H05K1/0271 , H05K3/28 , H05K2201/09681 , H05K2201/09781 , H05K2203/1572 , H01L2224/05599 , H01L2924/00012
摘要： A warpage preventing substrate is provided. A plurality of first and second conductive traces are respectively formed on a first surface and a second surface of a core layer of the substrate, each conductive trace having a terminal, and a plurality of first and second non-functional traces are respectively formed on the first and second surfaces of the core layer at area free of the conductive traces. The first non-functional traces are arranged in different density from the second non-functional traces in a manner that, stress generated from the first conductive traces and first non-functional traces counteracts stress generated from the second conductive traces and second non-functional traces, to thereby prevent warpage of the substrate and maintain flatness of the substrate.

36. 发明申请

US20100136266A1 Ornament Assembly that is Assembled and Disassembled Easily and Conveniently 审中-公开
标题翻译：装饰组装易于安装和拆卸
公开(公告)号：US20100136266A1
公开(公告)日：2010-06-03
申请号：US12326275
申请日：2008-12-02
申请人： Chin-Huang Chang
发明人： Chin-Huang Chang
IPC分类号： D04D7/10
CPC分类号： D04D7/10
摘要： An ornament assembly includes a support plate, a plurality of support posts mounted on the support plate, a plurality of first decorative strips mounted on the support posts, a plurality of second decorative strips mounted on the support posts, a plurality of fastening members mounted on the support posts and abutting the first decorative strips and the second decorative strips to fasten the first decorative strips and the second decorative strips on the support posts, and a connecting plate mounted on the support posts and abutting the first decorative strips and the second decorative strips to connect the first decorative strips and the second decorative strips. Thus, the ornament assembly can be assembled and disassembled easily, quickly and conveniently.
摘要翻译：装饰组件包括支撑板，安装在支撑板上的多个支撑柱，安装在支撑柱上的多个第一装饰条，安装在支撑柱上的多个第二装饰条，多个紧固件安装在所述支撑柱并且邻接所述第一装饰条和所述第二装饰条以将所述第一装饰条和所述第二装饰条紧固在所述支撑柱上，以及连接板，其安装在所述支撑柱上并且邻接所述第一装饰条和所述第二装饰条以连接第一装饰条和第二装饰条。因此，装饰组件可以容易，快速和方便地组装和拆卸。

37. 发明授权

US07266888B2 Method for fabricating a warpage-preventive circuit board 有权
标题翻译：防翘曲电路板的制造方法
公开(公告)号：US07266888B2
公开(公告)日：2007-09-11
申请号：US11043496
申请日：2005-01-25
申请人： Chin-Huang Chang , Chin-Tien Chiu , Chung-Lun Liu
发明人： Chin-Huang Chang , Chin-Tien Chiu , Chung-Lun Liu
IPC分类号： H05K3/02 , H05K3/10
CPC分类号： H01L23/49822 , H01L23/49838 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48227 , H01L2224/48228 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2924/3511 , H05K1/0271 , H05K3/28 , H05K2201/09663 , H05K2201/09781 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49155 , Y10T29/4916 , H01L2224/05599 , H01L2924/00012
摘要： A and method for fabricating a warpage-preventive circuit board is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.
摘要翻译：提供了一种制造防翘曲电路板的方法，其中在电绝缘芯层的表面上形成多个导电迹线，并且多个不连续的虚设电路区域设置在电绝缘性电路板的表面上，绝缘芯层在没有导电迹线的区域处，其中相邻的虚拟电路区域至少间隔开。在高温制造过程中，虚拟电路区域有助于降低热应力，并且汲取吸收虚拟电路区域的热膨胀，从而防止电路板翘曲和安装在电路板上的芯片的裂纹，使得屈服并且可以提高制造的半导体器件的可靠性。

38. 发明授权

US06720270B1 Method for reducing size of semiconductor unit in packaging process 失效
标题翻译：减少包装过程中半导体单元尺寸的方法
公开(公告)号：US06720270B1
公开(公告)日：2004-04-13
申请号：US09660753
申请日：2000-09-13
申请人： Chin-Huang Chang
发明人： Chin-Huang Chang
IPC分类号： H01L21302
CPC分类号： H01L24/96 , H01L21/6835 , H01L24/10 , H01L2221/6834 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/18161 , H01L2924/3025 , H01L2224/0401
摘要： The present invention provides different schemes for reducing the size (such as thickness) of at least a semiconductor unit (such as an IC chip) which is to be packaged. It replaces, in packaging at least a semiconductor unit, conventional grinding processes by etching schemes, particularly when the thickness of the semiconductor unit approximates an expected specification. The etching process may be embodied in a way that a semiconductor unit attached to a carrier such as a substrate, or placed onto a seating apparatus such as a chip tray, and properly shielded, is etched by means of using gas such as plasma, or beams of light. The semiconductor unit packaged according to the scheme provided by the present invention can thus be immunized against the failure resulting from die crack or back-side chipping.
摘要翻译：本发明提供了用于减少至少要包装的半导体单元（例如IC芯片）的尺寸（例如厚度）的不同方案。在将至少一个半导体单元封装在一起时，代替了通过蚀刻方案的常规研磨工艺，特别是当半导体单元的厚度接近预期规格时。蚀刻工艺可以通过使用诸如等离子体之类的气体来蚀刻附接到诸如衬底的载体的半导体单元或放置在诸如芯片托盘的座位装置上并被适当地屏蔽的半导体单元的方式，或者光束。因此，可以根据本发明提供的方案包装的半导体单元免受由于模头裂纹或背面切屑引起的故障的影响。

39. 发明授权

US08896130B2 Multi-chip stack structure and method for fabricating the same 有权
标题翻译：多芯片堆叠结构及其制造方法
公开(公告)号：US08896130B2
公开(公告)日：2014-11-25
申请号：US12266830
申请日：2008-11-07
申请人： Chung-Lun Liu , Jung-Pin Huang , Yi-Feng Chang , Chin-Huang Chang
发明人： Chung-Lun Liu , Jung-Pin Huang , Yi-Feng Chang , Chin-Huang Chang
IPC分类号： H01L23/49 , H01L23/31 , H01L25/065 , H01L23/00 , H01L25/00 , H01L25/18
CPC分类号： H01L25/50 , H01L21/56 , H01L23/3107 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L25/0657 , H01L25/18 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83 , H01L2224/858 , H01L2224/8592 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/15313 , H01L2924/15321 , H01L2924/15323 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficulty.
摘要翻译：提供了一种多芯片堆叠结构及其制造方法。制造多芯片堆叠结构的方法包括通过使用阶梯状方式将包括多个第一芯片的第一芯片组布置在芯片载体上，将第二芯片设置在第一芯片组的顶部上的第一芯片上，通过接合线将第一芯片组和第二芯片电连接到芯片载体上，使用薄膜覆盖线（FOW）来在第一芯片和第二芯片之间设置绝缘膜，其中绝缘膜覆盖部分在第一组的顶部和第二芯片的至少一部分上的第一芯片的接合线的端部，并且通过接合线将第三芯片电连接到芯片载体，从而防止直接布置在第一芯片上第二芯片的平面尺寸远远小于现有技术中的第一芯片的平面尺寸，这增加了整个结构的高度并增加了布线粘合难度。

40. 发明授权

US07339199B2 Semiconductor package including light emitter and IC 有权
标题翻译：半导体封装包括发光器和IC
公开(公告)号：US07339199B2
公开(公告)日：2008-03-04
申请号：US11237137
申请日：2005-09-28
申请人： Wei Lung Lu , Cheng Jen Liu , Chin-Huang Chang , Yi-Feng Chang
发明人： Wei Lung Lu , Cheng Jen Liu , Chin-Huang Chang , Yi-Feng Chang
IPC分类号： H01L29/22
CPC分类号： H01L25/167 , H01L2224/48091 , H01L2224/48227 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00014 , H01L2924/00012
摘要： The is to disclose a semiconductor package featuring inclusion of light emitter(s) providing light to indicate the states of the semiconductor package as a whole and/or the chip(s) therein. The light emitter is in an original state or flashing state or emitting state according to the states of the semiconductor package as a whole and/or the chip(s). The semiconductor package includes a carrier and a shield structure in addition to the light emitter. The chip and at least part of the carrier are covered by the shield structure. The light emitter may be partially or fully covered or sealed by the shield structure. The light emitter may also be partially or fully exposed. The shield structure is such that the light provided by the light emitter sealed therein can pass therethrough to reach the outside thereof, thereby the states of the semiconductor package as a whole and/or the chip(s) can be recognized from the outside of the semiconductor package.
摘要翻译：公开了一种包括提供光的发光体的半导体封装，以指示半导体封装作为整体的状态和/或其中的芯片。根据半导体封装整体的状态和/或芯片，光发射器处于原始状态或闪烁状态或发光状态。除了发光体之外，半导体封装还包括载体和屏蔽结构。芯片和载体的至少一部分被屏蔽结构覆盖。光发射器可以被屏蔽结构部分地或完全地覆盖或密封。光发射器也可以部分地或完全暴露。屏蔽结构使得由其中密封的发光器提供的光可以通过其中以到达其外部，从而可以从外部识别半导体封装的整体状态和/或芯片半导体封装。

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