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1. 发明授权

US07339199B2 Semiconductor package including light emitter and IC 有权
标题翻译：半导体封装包括发光器和IC
公开(公告)号：US07339199B2
公开(公告)日：2008-03-04
申请号：US11237137
申请日：2005-09-28
申请人： Wei Lung Lu , Cheng Jen Liu , Chin-Huang Chang , Yi-Feng Chang
发明人： Wei Lung Lu , Cheng Jen Liu , Chin-Huang Chang , Yi-Feng Chang
IPC分类号： H01L29/22
CPC分类号： H01L25/167 , H01L2224/48091 , H01L2224/48227 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00014 , H01L2924/00012
摘要： The is to disclose a semiconductor package featuring inclusion of light emitter(s) providing light to indicate the states of the semiconductor package as a whole and/or the chip(s) therein. The light emitter is in an original state or flashing state or emitting state according to the states of the semiconductor package as a whole and/or the chip(s). The semiconductor package includes a carrier and a shield structure in addition to the light emitter. The chip and at least part of the carrier are covered by the shield structure. The light emitter may be partially or fully covered or sealed by the shield structure. The light emitter may also be partially or fully exposed. The shield structure is such that the light provided by the light emitter sealed therein can pass therethrough to reach the outside thereof, thereby the states of the semiconductor package as a whole and/or the chip(s) can be recognized from the outside of the semiconductor package.
摘要翻译：公开了一种包括提供光的发光体的半导体封装，以指示半导体封装作为整体的状态和/或其中的芯片。根据半导体封装整体的状态和/或芯片，光发射器处于原始状态或闪烁状态或发光状态。除了发光体之外，半导体封装还包括载体和屏蔽结构。芯片和载体的至少一部分被屏蔽结构覆盖。光发射器可以被屏蔽结构部分地或完全地覆盖或密封。光发射器也可以部分地或完全暴露。屏蔽结构使得由其中密封的发光器提供的光可以通过其中以到达其外部，从而可以从外部识别半导体封装的整体状态和/或芯片半导体封装。

2. 发明授权

US08264607B2 Method of sampling phase calibration and device thereof 有权
标题翻译：相位校准取样方法及其装置
公开(公告)号：US08264607B2
公开(公告)日：2012-09-11
申请号：US12883182
申请日：2010-09-16
申请人： Chian-Wen Chen , Wei-Lung Lu , Jui-Yao Lee
发明人： Chian-Wen Chen , Wei-Lung Lu , Jui-Yao Lee
IPC分类号： H03L7/00
CPC分类号： H03M1/1255
摘要： A method of sampling phase calibration and a device thereof is suitable for an analog-to-digital converter and phase lock loop (ADC-PLL). The ADC-PLL conducts sampling on a periodic analog signal according to a sampling phase so as to produce a plurality of digital signals. The sampling phase calibration device includes a storage unit, a motion-detecting unit and a control unit. The motion-detecting unit is to calculate the number of motion data corresponding to a sampling phase. The control unit is coupled to the motion-detecting unit for changing the sampling phase so as to obtain the number of motion data corresponding to each sampling phase and selecting the sampling phase corresponding to the minimum number of motion data as an optimal sampling phase. The ADC-PLL can correctly sample an analog signal by using the optimal sampling phase and reduce the influence of clock jitter to the minimum.
摘要翻译：相位校准的采样方法及其装置适用于模数转换器和锁相环（ADC-PLL）。 ADC-PLL根据采样相位对周期性模拟信号进行采样，以产生多个数字信号。采样相位校准装置包括存储单元，运动检测单元和控制单元。运动检测单元计算与采样相对应的运动数据的数量。控制单元耦合到运动检测单元，用于改变采样相位，以获得对应于每个采样相位的运动数据的数量，并且将与最小运动数据数相对应的采样相位选择为最佳采样相位。 ADC-PLL可以通过使用最佳采样相位对模拟信号进行正确采样，并将时钟抖动的影响降至最低。

3. 发明申请

US20110304768A1 METHOD OF SAMPLING PHASE CALIBRATION AND DEVICE THEREOF 有权
标题翻译：采样相位校准方法及其装置
公开(公告)号：US20110304768A1
公开(公告)日：2011-12-15
申请号：US12883182
申请日：2010-09-16
申请人： Chian-Wen Chen , Wei-Lung Lu , Jui-Yao Lee
发明人： Chian-Wen Chen , Wei-Lung Lu , Jui-Yao Lee
IPC分类号： H04N5/12
CPC分类号： H03M1/1255
摘要： A method of sampling phase calibration and a device thereof is suitable for an analog-to-digital converter and phase lock loop (ADC-PLL). The ADC-PLL conducts sampling on a periodic analog signal according to a sampling phase so as to produce a plurality of digital signals. The sampling phase calibration device includes a storage unit, a motion-detecting unit and a control unit. The motion-detecting unit is to calculate the number of motion data corresponding to a sampling phase. The control unit is coupled to the motion-detecting unit for changing the sampling phase so as to obtain the number of motion data corresponding to each sampling phase and selecting the sampling phase corresponding to the minimum number of motion data as an optimal sampling phase. The ADC-PLL can correctly sample an analog signal by using the optimal sampling phase and reduce the influence of clock jitter to the minimum.
摘要翻译：相位校准的采样方法及其装置适用于模数转换器和锁相环（ADC-PLL）。 ADC-PLL根据采样相位对周期性模拟信号进行采样，以产生多个数字信号。采样相位校准装置包括存储单元，运动检测单元和控制单元。运动检测单元计算与采样相对应的运动数据的数量。控制单元耦合到运动检测单元，用于改变采样相位，以获得对应于每个采样相位的运动数据的数量，并且将与最小运动数据数相对应的采样相位选择为最佳采样相位。 ADC-PLL可以通过使用最佳采样相位对模拟信号进行正确采样，并将时钟抖动的影响降至最低。

4. 发明申请

US20080230878A1 Leadframe based flip chip semiconductor package and lead frame thereof 审中-公开
标题翻译：基于引线框的倒装芯片半导体封装及其引线框架
公开(公告)号：US20080230878A1
公开(公告)日：2008-09-25
申请号：US12077489
申请日：2008-03-19
申请人： Wei-Lung Lu , Chih-Nan Lin , Shih-Kuang Chiu , Chin-Te Chen
发明人： Wei-Lung Lu , Chih-Nan Lin , Shih-Kuang Chiu , Chin-Te Chen
IPC分类号： H01L23/495
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/49541 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： A flip chip semiconductor package is disclosed according to the present invention, the flip chip semiconductor package comprises a chip that is mounted on and electrically connects to a leadframe via a plurality of solder bumps by means of flip chip, and an encapsulate that encapsulates the chip, the plurality of solder bumps, and the leadframe, wherein, the leadframe further comprises a plurality of leads and a ground plane that is located between the plurality of leads, and also a slit is formed on the ground plane, and then a molding compound that makes up the encapsulant should be capable of filling within the slit, thus to enhance the adhesion between the ground plane and the encapsulant, and then avoid delamination between the ground plane and the encapsulant in subsequent thermal cycle processes, thereby increasing the reliability of fabricated products.
摘要翻译：根据本发明公开了一种倒装芯片半导体封装，所述倒装芯片半导体封装包括通过倒装芯片经由多个焊料凸块安装在引线框架上并与其电连接的芯片，以及封装芯片多个焊料凸块和引线框架，其中引线框还包括多个引线和位于多个引线之间的接地平面，并且在接地平面上形成狭缝，然后形成模塑料这样构成的密封剂应该能够在狭缝内填充，从而增强接地层与密封剂之间的密合性，然后避免在随后的热循环过程中接地层与密封剂之间的分层，从而提高制造的可靠性产品。

5. 发明申请

US20060071220A1 Semiconductor package including light emitter and IC 有权
标题翻译：半导体封装包括发光器和IC
公开(公告)号：US20060071220A1
公开(公告)日：2006-04-06
申请号：US11237137
申请日：2005-09-28
申请人： Wei Lung Lu , Cheng Jen Liu , Chin-Huang Chang , Yi-Feng Chang
发明人： Wei Lung Lu , Cheng Jen Liu , Chin-Huang Chang , Yi-Feng Chang
IPC分类号： H01L31/12
CPC分类号： H01L25/167 , H01L2224/48091 , H01L2224/48227 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00014 , H01L2924/00012
摘要： The is to disclose a semiconductor package featuring inclusion of light emitter(s) providing light to indicate the states of the semiconductor package as a whole and/or the chip(s) therein. The light emitter is in an original state or flashing state or emitting state according to the states of the semiconductor package as a whole and/or the chip(s). The semiconductor package includes a carrier and a shield structure in addition to the light emitter. The chip and at least part of the carrier are covered by the shield structure. The light emitter may be partially or fully covered or sealed by the shield structure. The light emitter may also be partially or fully exposed. The shield structure is such that the light provided by the light emitter sealed therein can pass therethrough to reach the outside thereof, thereby the states of the semiconductor package as a whole and/or the chip(s) can be recognized from the outside of the semiconductor package.
摘要翻译：公开了一种包括提供光的发光体的半导体封装，以指示半导体封装作为整体的状态和/或其中的芯片。根据半导体封装整体的状态和/或芯片，光发射器处于原始状态或闪烁状态或发光状态。除了发光体之外，半导体封装还包括载体和屏蔽结构。芯片和载体的至少一部分被屏蔽结构覆盖。光发射器可以被屏蔽结构部分地或完全地覆盖或密封。光发射器也可以部分地或完全暴露。屏蔽结构使得由其中密封的发光器提供的光可以通过其中以到达其外部，从而可以从外部识别半导体封装的整体状态和/或芯片半导体封装。

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