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31. 发明授权

US06746966B1 Method to solve alignment mark blinded issues and a technology for application of semiconductor etching at a tiny area 失效
标题翻译：解决对准标记盲目问题的方法和在微小区域应用半导体蚀刻技术
公开(公告)号：US06746966B1
公开(公告)日：2004-06-08
申请号：US10353229
申请日：2003-01-28
申请人： Chung-Long Chang , Henry Lo , Shang-Ting Tsai , Yu-Liang Lin
发明人： Chung-Long Chang , Henry Lo , Shang-Ting Tsai , Yu-Liang Lin
IPC分类号： H01L21302
CPC分类号： H01L21/31111 , G03F9/7076 , G03F9/708 , G03F9/7084
摘要： A method of unblinding an alignment mark comprising the following steps. A substrate having a cell area and an alignment mark within an alignment area is provided. An STI trench is formed into the substrate within the cell area. A silicon oxide layer is formed over the substrate, filling the STI trench and the alignment mark. The silicon oxide layer is planarized to form a planarized STI within the STI trench and leaving silicon oxide within the alignment mark to form a blinded alignment mark. A wet chemical etchant is applied within the alignment mark area over the blinded alignment mark to at least partially remove the silicon oxide within the alignment mark. The remaining silicon oxide is removed from within the blinded alignment mark to unblind the alignment mark. A drop etcher apparatus is also disclosed.
摘要翻译：一种解开对准标记的方法，包括以下步骤。提供了在对准区域内具有单元区域和对准标记的基板。在沟槽区内形成STI沟槽。在衬底上形成氧化硅层，填充STI沟槽和对准标记。将氧化硅层平坦化以在STI沟槽内形成平坦化的STI，并使对准标记内的氧化硅形成盲目的对准标记。湿法化学蚀刻剂施加在对准标记区域内的盲目对准标记上，以至少部分地去除对准标记内的氧化硅。剩余的氧化硅从盲目的对准标记中移除，以对准对准标记。还公开了一种滴蚀蚀刻装置。

32. 发明授权

US06737310B2 Self-aligned process for a stacked gate RF MOSFET device 失效
标题翻译：堆叠栅极RF MOSFET器件的自对准工艺
公开(公告)号：US06737310B2
公开(公告)日：2004-05-18
申请号：US10236536
申请日：2002-09-06
申请人： Chaochieh Tsai , Chung-Long Chang , Jui-Yu Chang , Shyh-Chyi Wong
发明人： Chaochieh Tsai , Chung-Long Chang , Jui-Yu Chang , Shyh-Chyi Wong
IPC分类号： H01L218238
CPC分类号： H01L21/7681 , H01L21/76897 , H01L21/823475 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A process for fabricating an RF type, MOSFET device, concentrating on reducing performance degrading gate resistance, has been developed. The process features formation of a stacked gate structure, comprised of a metal gate contact structure located directly overlying a portion of an underlying polysilicon gate structure, in a region in which the polysilicon gate structure is located on an active device region of a semiconductor substrate. Subsequent formation of an overlying metal interconnect structure, results in reduced gate resistance due to the direct vertical conductive path from the metal interconnect structure to the polysilicon gate structure, through the metal gate contact structure. A novel process sequence, requiring no photolithographic processing, is used to self-align the metal gate contact structure to the underlying polysilicon gate structure.
摘要翻译：已经开发了一种用于制造RF型MOSFET器件的方法，其集中在降低性能降低栅极电阻。该工艺特征是在多晶硅栅极结构位于半导体衬底的有源器件区域上的区域中形成层叠栅极结构，该栅极结构由位于下面的多晶硅栅极结构的一部分直接覆盖的金属栅极接触结构构成。随后形成上覆的金属互连结构，由于通过金属栅极接触结构从金属互连结构到多晶硅栅极结构的直接垂直导电路径，导致栅极电阻降低。使用不需要光刻处理的新颖工艺顺序来将金属栅极接触结构自对准到下面的多晶硅栅极结构。

33. 发明授权

US06613623B1 High fMAX deep submicron MOSFET 有权
标题翻译：高fMAX深亚微米MOSFET
公开(公告)号：US06613623B1
公开(公告)日：2003-09-02
申请号：US09932730
申请日：2001-08-20
申请人： Chao-Chieh Tsai , Shyh-Chyi Wong , Chung-Long Chang
发明人： Chao-Chieh Tsai , Shyh-Chyi Wong , Chung-Long Chang
IPC分类号： H01L21336
CPC分类号： H01L21/28114 , H01L21/76819 , H01L21/76895 , H01L29/42376 , H01L29/4238 , H01L29/665
摘要： A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET. Whereby the width of the metal gate portion reduces Rg and increases the fMAX of the high fMAX deep submicron MOSFET.
摘要翻译：一种形成高fMAX深亚微米MOSFET的方法，包括以下步骤。提供其上形成有MOSFET的衬底。 MOSFET具有源极和漏极，并且在栅极上方包括硅化物部分。在衬底和MOSFET上形成第一ILD层。将第一ILD层平坦化以在栅电极上露出硅化物部分。金属栅极部分形成在平坦化的第一ILD层之上并且在栅电极上方的硅化物部分之上。金属栅极部分的宽度基本上大于栅电极上的硅化物部分的宽度。第二ILD层形成在金属栅极部分和第一ILD层上。通过与金属栅极部分接触的第二ILD层形成第一金属接触，并且通过接触漏极的第二和第一ILD层形成第二金属接触，从而完成高fMAX深亚微米MOSFET的形成。由此金属栅极部分的宽度减小Rg并增加高fMAX深亚微米MOSFET的fMAX。

34. 发明授权

US08237209B2 Capacitors integrated with metal gate formation 有权
标题翻译：电容器与金属栅极结合
公开(公告)号：US08237209B2
公开(公告)日：2012-08-07
申请号：US13215988
申请日：2011-08-23
申请人： Chung-Long Chang , David Ding-Chung Lu , Chia-Yi Chen , I-Lu Wu
发明人： Chung-Long Chang , David Ding-Chung Lu , Chia-Yi Chen , I-Lu Wu
IPC分类号： H01L21/108
CPC分类号： H01L27/11568 , H01L23/5223 , H01L27/0629 , H01L27/105 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate and a MIM capacitor over the substrate. The MIM capacitor includes a bottom plate, an insulating layer over the bottom plate, and a top plate over the insulating layer. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate and a metal-containing gate electrode free from polysilicon on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material and has a same thickness as the bottom plate.
摘要翻译：提供了包括具有增加的电容和改善的电性能的电容器的半导体结构。半导体结构包括衬底和MIM电容器。 MIM电容器包括底板，底板上的绝缘层和绝缘层上的顶板。该半导体结构还包括一个MOS器件，该MOS器件包括在该衬底上的一个栅极电介质和一个在栅极电介质上不含多晶硅的含金属的栅电极，其中含金属的栅电极由相同的材料形成并且具有与底板。

35. 发明申请

US20110309420A1 Capacitors Integrated with Metal Gate Formation 有权
标题翻译：电容器与金属门形成集成
公开(公告)号：US20110309420A1
公开(公告)日：2011-12-22
申请号：US13215988
申请日：2011-08-23
申请人： Chung-Long Chang , David Ding-Chung Lu , Chia-Yi Chen , I-Lu Wu
发明人： Chung-Long Chang , David Ding-Chung Lu , Chia-Yi Chen , I-Lu Wu
IPC分类号： H01L27/07
CPC分类号： H01L27/11568 , H01L23/5223 , H01L27/0629 , H01L27/105 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate and a MIM capacitor over the substrate. The MIM capacitor includes a bottom plate, an insulating layer over the bottom plate, and a top plate over the insulating layer. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate and a metal-containing gate electrode free from polysilicon on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material and has a same thickness as the bottom plate.
摘要翻译：提供了包括具有增加的电容和改善的电性能的电容器的半导体结构。半导体结构包括衬底和MIM电容器。 MIM电容器包括底板，底板上的绝缘层和绝缘层上的顶板。该半导体结构还包括一个MOS器件，该MOS器件包括在该衬底上的一个栅极电介质和一个在栅极电介质上不含多晶硅的含金属的栅电极，其中含金属的栅电极由相同的材料形成并且具有与底板。

36. 发明授权

US07760144B2 Antennas integrated in semiconductor chips 失效
标题翻译：天线集成在半导体芯片中
公开(公告)号：US07760144B2
公开(公告)日：2010-07-20
申请号：US12185591
申请日：2008-08-04
申请人： Chung-Long Chang , David Ding-Chung Lu , Shine Chung
发明人： Chung-Long Chang , David Ding-Chung Lu , Shine Chung
IPC分类号： H01Q1/38 , H01Q1/24
CPC分类号： H01Q23/00 , H01L23/585 , H01L23/66 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L2223/6677 , H01L2224/05624 , H01L2224/05647 , H01L2224/48091 , H01L2224/48145 , H01L2224/48195 , H01L2224/484 , H01L2225/06506 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01Q1/38 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit structure includes a semiconductor chip including a top surface, a bottom surface, and a side surface; a metal seal ring adjacent the side surface; and an antenna including a seal-ring antenna. The seal-ring antenna includes at least a portion of the metal seal ring.
摘要翻译：集成电路结构包括：半导体芯片，包括顶表面，底表面和侧表面; 靠近侧面的金属密封环; 以及包括密封环天线的天线。所述密封环天线包括所述金属密封环的至少一部分。

37. 发明申请

US20100026601A1 Antennas Integrated in Semiconductor Chips 失效
标题翻译：天线集成在半导体芯片中
公开(公告)号：US20100026601A1
公开(公告)日：2010-02-04
申请号：US12185591
申请日：2008-08-04
申请人： Chung-Long Chang , David Ding-Chung Lu , Shine Chung
发明人： Chung-Long Chang , David Ding-Chung Lu , Shine Chung
IPC分类号： H01Q19/10
CPC分类号： H01Q23/00 , H01L23/585 , H01L23/66 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L2223/6677 , H01L2224/05624 , H01L2224/05647 , H01L2224/48091 , H01L2224/48145 , H01L2224/48195 , H01L2224/484 , H01L2225/06506 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01Q1/38 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit structure includes a semiconductor chip including a top surface, a bottom surface, and a side surface; a metal seal ring adjacent the side surface; and an antenna including a seal-ring antenna. The seal-ring antenna includes at least a portion of the metal seal ring.
摘要翻译：集成电路结构包括：半导体芯片，包括顶表面，底表面和侧表面; 靠近侧面的金属密封环; 以及包括密封环天线的天线。密封环天线包括金属密封环的至少一部分。

38. 发明授权

US07612984B2 Layout for capacitor pair with high capacitance matching 有权
标题翻译：具有高电容匹配的电容器对的布局
公开(公告)号：US07612984B2
公开(公告)日：2009-11-03
申请号：US11591643
申请日：2006-11-01
申请人： Chia-Yi Chen , Chung-Long Chang , Chih-Ping Chao
发明人： Chia-Yi Chen , Chung-Long Chang , Chih-Ping Chao
IPC分类号： H01G4/06 , H01G4/005
CPC分类号： H01L27/0805 , H01G4/38 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes a capacitor array, which includes unit capacitors arranged in rows and columns, wherein each unit capacitor is formed of two electrically insulated capacitor plates. The unit capacitors include at least one first unit capacitor in each row and in each column of the capacitor array; the at least one first unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have. The unit capacitors further include at least one second unit capacitor in each row and in each column of the capacitor array, wherein the at least one second unit is interconnected and evenly distributed throughout the array.
摘要翻译：集成电路装置包括电容器阵列，其包括以行和列排列的单位电容器，其中每个单位电容器由两个电绝缘电容器板形成。单位电容器包括电容器阵列的每一行和每列中的至少一个第一单位电容器; 所述至少一个第一单元电容器互连，其中所述电容器阵列的每一行包括与其它行和列具有相同数量的所述至少一个第一单位电容器，并且其中所述电容器阵列的每列包括相同数量的其他行和列具有至少一个第一单位电容器。单元电容器还包括在电容器阵列的每一列和每列中的至少一个第二单位电容器，其中该至少一个第二单元互连并均匀分布在整个阵列中。

39. 发明申请

US20050206469A1 Interdigitated capacitor and method for fabrication therof 有权
标题翻译：交叉电容器及其制造方法
公开(公告)号：US20050206469A1
公开(公告)日：2005-09-22
申请号：US10804899
申请日：2004-03-19
申请人： Wen-Chin Lin , Denny Tang , Li-Shyue Lai , Chung-Long Chang , Chun-Hon Chen
发明人： Wen-Chin Lin , Denny Tang , Li-Shyue Lai , Chung-Long Chang , Chun-Hon Chen
IPC分类号： H01L23/522 , H01P1/36
CPC分类号： H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A capacitor for use within a microelectronic product employs a first capacitor plate layer that includes a first series of horizontally separated and interconnected tines. A capacitor dielectric layer separates the first capacitor plate layer from a second capacitor plate layer. The second capacitor plate layer includes a second series of horizontally separated and interconnected tines horizontally interdigitated with the first series of horizontally separated and interconnected tines. The capacitor is formed employing a self-aligned method and the capacitor dielectric layer is formed in a serpentine shape.
摘要翻译：在微电子产品中使用的电容器采用第一电容器板层，其包括第一系列水平分离和互连的尖齿。电容器电介质层将第一电容器板层与第二电容器板层分开。第二电容器板层包括与第一系列水平分离和互相联接的齿水平地交叉指向的第二系列水平分离和互连的齿。使用自对准方法形成电容器，并且电容器介电层形成为蛇形形状。

40. 发明申请

US20050077581A1 Metal-over-metal devices and the method for manufacturing same 有权
公开(公告)号：US20050077581A1
公开(公告)日：2005-04-14
申请号：US10683900
申请日：2003-10-10
申请人： Chung-Long Chang , Chun-Hon Chen
发明人： Chung-Long Chang , Chun-Hon Chen
IPC分类号： H01L23/522 , H01L29/76
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A metal-over-metal (MOM) device and the method for manufacturing same is provided. The device has at least one device cell on a first layer comprising a frame piece and a center piece surrounded by the frame piece. The center piece has a cross-shape center portion defining four quadrants of space between the frame and center pieces. The center piece has one or more center fingers each extending from at least one of the four ends thereof within a quadrant. The frame piece also has one or more frame fingers extending therefrom, each being in at least one quadrant and not being overlapped with the center finger in the same quadrant.

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