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1. 发明授权

US06746966B1 Method to solve alignment mark blinded issues and a technology for application of semiconductor etching at a tiny area 失效
标题翻译：解决对准标记盲目问题的方法和在微小区域应用半导体蚀刻技术
公开(公告)号：US06746966B1
公开(公告)日：2004-06-08
申请号：US10353229
申请日：2003-01-28
申请人： Chung-Long Chang , Henry Lo , Shang-Ting Tsai , Yu-Liang Lin
发明人： Chung-Long Chang , Henry Lo , Shang-Ting Tsai , Yu-Liang Lin
IPC分类号： H01L21302
CPC分类号： H01L21/31111 , G03F9/7076 , G03F9/708 , G03F9/7084
摘要： A method of unblinding an alignment mark comprising the following steps. A substrate having a cell area and an alignment mark within an alignment area is provided. An STI trench is formed into the substrate within the cell area. A silicon oxide layer is formed over the substrate, filling the STI trench and the alignment mark. The silicon oxide layer is planarized to form a planarized STI within the STI trench and leaving silicon oxide within the alignment mark to form a blinded alignment mark. A wet chemical etchant is applied within the alignment mark area over the blinded alignment mark to at least partially remove the silicon oxide within the alignment mark. The remaining silicon oxide is removed from within the blinded alignment mark to unblind the alignment mark. A drop etcher apparatus is also disclosed.
摘要翻译：一种解开对准标记的方法，包括以下步骤。提供了在对准区域内具有单元区域和对准标记的基板。在沟槽区内形成STI沟槽。在衬底上形成氧化硅层，填充STI沟槽和对准标记。将氧化硅层平坦化以在STI沟槽内形成平坦化的STI，并使对准标记内的氧化硅形成盲目的对准标记。湿法化学蚀刻剂施加在对准标记区域内的盲目对准标记上，以至少部分地去除对准标记内的氧化硅。剩余的氧化硅从盲目的对准标记中移除，以对准对准标记。还公开了一种滴蚀蚀刻装置。

2. 发明授权

US07125521B2 Method to solve alignment mark blinded issues and technology for application of semiconductor etching at a tiny area 有权
标题翻译：解决对准标记盲法问题的方法和在微小区域应用半导体蚀刻技术
公开(公告)号：US07125521B2
公开(公告)日：2006-10-24
申请号：US10831894
申请日：2004-04-26
申请人： Chung-Long Chang , Jui-Cheng Lo , Shang-Ting Tsai , Yu-Liang Lin
发明人： Chung-Long Chang , Jui-Cheng Lo , Shang-Ting Tsai , Yu-Liang Lin
IPC分类号： B01L3/02 , G01N1/10 , G01N1/32
CPC分类号： H01L21/31111 , G03F9/7076 , G03F9/708 , G03F9/7084
摘要： A method of unblinding an alignment mark comprising the following steps. A substrate having a cell area and an alignment mark within an alignment area is provided. An STI trench is formed into the substrate within the cell area. A silicon oxide layer is formed over the substrate, filling the STI trench and the alignment mark. The silicon oxide layer is planarized to form a planarized STI within the STI trench and leaving silicon oxide within the alignment mark to form a blinded alignment mark. A wet chemical etchant is applied within the alignment mark area over the blinded alignment mark to at least partially remove the silicon oxide within the alignment mark. The remaining silicon oxide is removed from within the blinded alignment mark to unblind the alignment mark. A drop etcher apparatus is also disclosed.
摘要翻译：一种解开对准标记的方法，包括以下步骤。提供了在对准区域内具有单元区域和对准标记的基板。在沟槽区内形成STI沟槽。在衬底上形成氧化硅层，填充STI沟槽和对准标记。将氧化硅层平坦化以在STI沟槽内形成平坦化的STI，并使对准标记内的氧化硅形成盲目的对准标记。湿法化学蚀刻剂施加在对准标记区域内的盲目对准标记上，以至少部分地去除对准标记内的氧化硅。剩余的氧化硅从盲目的对准标记中移除，以对准对准标记。还公开了一种滴蚀蚀刻装置。

3. 发明授权

US07338909B2 Micro-etching method to replicate alignment marks for semiconductor wafer photolithography 有权
标题翻译：用于复制半导体晶片光刻的对准标记的微蚀刻方法
公开(公告)号：US07338909B2
公开(公告)日：2008-03-04
申请号：US10872238
申请日：2004-06-18
申请人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Su , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Che Wang
发明人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Su , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Che Wang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L23/544 , H01L21/31111 , H01L21/67282 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to selectively etch the material layer overlying the targeted etching portion.
摘要翻译：一种用于局部蚀刻衬底区域的方法和装置，该方法包括提供包含工艺表面的衬底; 在工艺表面上沉积材料层; 以及施加湿蚀刻剂以覆盖所述工艺表面的目标蚀刻部分，同时排除相邻的周围区域以选择性地蚀刻覆盖所述目标蚀刻部分的所述材料层。

4. 发明申请

US20050282396A1 Micro-etching method to replicate alignment marks for semiconductor wafer photolithography 有权
标题翻译：用于复制半导体晶片光刻的对准标记的微蚀刻方法
公开(公告)号：US20050282396A1
公开(公告)日：2005-12-22
申请号：US10872238
申请日：2004-06-18
申请人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Wu , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Wang
发明人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Wu , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Wang
IPC分类号： H01L21/00 , H01L21/302 , H01L21/311 , H01L21/336 , H01L21/461 , H01L23/544
CPC分类号： H01L23/544 , H01L21/31111 , H01L21/67282 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to selectively etch the material layer overlying the targeted etching portion.
摘要翻译：一种用于局部蚀刻衬底区域的方法和装置，该方法包括提供包含工艺表面的衬底; 在工艺表面上沉积材料层; 以及施加湿蚀刻剂以覆盖所述工艺表面的目标蚀刻部分，同时排除相邻的周围区域以选择性地蚀刻覆盖所述目标蚀刻部分的所述材料层。

5. 发明授权

US08169014B2 Interdigitated capacitive structure for an integrated circuit 有权
标题翻译：用于集成电路的交叉电容结构
公开(公告)号：US08169014B2
公开(公告)日：2012-05-01
申请号：US11328502
申请日：2006-01-09
申请人： Yueh-You Chen , Chung-Long Chang , Chih-Ping Chao
发明人： Yueh-You Chen , Chung-Long Chang , Chih-Ping Chao
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： System and method for an improved interdigitated capacitive structure for an integrated circuit. A preferred embodiment comprises a first layer of a sequence of substantially parallel interdigitated strips, each strip of either a first polarity or a second polarity, the sequence alternating between a strip of the first polarity and a strip of the second polarity. A first dielectric layer is deposited over each strip of the first layer of strips. A first extension layer of a sequence of substantially interdigitated extension strips is deposited over the first dielectric layer, each extension strip deposited over a strip of the first layer of the opposite polarity. A first sequence of vias is coupled to the first extension layer, each via deposited over an extension strip of the same polarity. A second layer of a sequence of substantially parallel interdigitated strips can be coupled to the first sequence of vias.
摘要翻译：用于集成电路的改进的互指电容结构的系统和方法。优选实施例包括基本上平行的叉指序列序列的第一层，每个条带具有第一极性或第二极性，该序列在第一极性的条带和第二极性的条之间交替。第一介电层沉积在第一层条带的每条上。基本上交错的延伸条的序列的第一延伸层沉积在第一介电层上，每个延伸条沉积在具有相反极性的第一层的条上。通孔的第一序列耦合到第一延伸层，每个通孔沉积在相同极性的延伸条上。基本上平行的叉指序列序列的第二层可以耦合到第一序列通孔。

6. 发明申请

US20090212392A1 Capacitor Pairs with Improved Mismatch Performance 有权
标题翻译：具有改进的不匹配性能的电容对
公开(公告)号：US20090212392A1
公开(公告)日：2009-08-27
申请号：US12463949
申请日：2009-05-11
申请人： Chia-Yi Chen , Chung-Long Chang , Chih-Ping Chao
发明人： Chia-Yi Chen , Chung-Long Chang , Chih-Ping Chao
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors and the second unit capacitors have equal numbers of unit capacitors. The first unit capacitors and the second unit capacitors are arranged in an array with rows and columns and placed in an alternating pattern in each row and each column. The first and the second unit capacitors each have a total number greater than two.
摘要翻译：半导体器件包括：第一电容器，包括彼此互连的多个第一单位电容器，每个具有第一单位电容; 以及包括彼此互连的多个第二单位电容器的第二电容器，每个具有第二单位电容，其中所述第一单位电容器和所述第二单位电容器具有相等数目的单位电容器。第一单元电容器和第二单元电容器以具有行和列的阵列排列并且以每行和每列置于交替图案中。第一和第二单元电容器的总数大于2。

7. 发明授权

US07545022B2 Capacitor pairs with improved mismatch performance 有权
标题翻译：具有改善失配性能的电容对
公开(公告)号：US07545022B2
公开(公告)日：2009-06-09
申请号：US11591644
申请日：2006-11-01
申请人： Chia-Yi Chen , Chung-Long Chang , Chih-Ping Chao
发明人： Chia-Yi Chen , Chung-Long Chang , Chih-Ping Chao
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors and the second unit capacitors have equal numbers of unit capacitors. The first unit capacitors and the second unit capacitors are arranged in an array with rows and columns and placed in an alternating pattern in each row and each column. The first and the second unit capacitors each have a total number greater than two.
摘要翻译：半导体器件包括：第一电容器，包括彼此互连的多个第一单位电容器，每个具有第一单位电容; 以及包括彼此互连的多个第二单位电容器的第二电容器，每个具有第二单位电容，其中所述第一单位电容器和所述第二单位电容器具有相等数目的单位电容器。第一单元电容器和第二单元电容器以具有行和列的阵列排列并且以每行和每列置于交替图案中。第一和第二单元电容器的总数大于2。

8. 发明申请

US20060180895A1 Capacitor device with vertically arranged capacitor regions of various kinds 有权
标题翻译：具有各种垂直排列的电容器区域的电容器件
公开(公告)号：US20060180895A1
公开(公告)日：2006-08-17
申请号：US11055933
申请日：2005-02-11
申请人： Yueh-You Chen , Chung-Long Chang , Chih-Ping Chao , Chun-Hong Chen
发明人： Yueh-You Chen , Chung-Long Chang , Chih-Ping Chao , Chun-Hong Chen
IPC分类号： H01L29/93
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0805 , H01L27/0808 , H01L28/40 , H01L29/93 , H01L2924/0002 , H01L2924/00
摘要： A capacitor device selectively combines MOM, MIM and varactor regions in the same layout area of an IC. Two or more types of capacitor regions arranged vertically on a substrate to form the capacitor device. This increase the capacitance per unit of the capacitor device, without occupying an extra layout area.
摘要翻译：电容器器件在IC的相同布局区域中选择性地组合MOM，MIM和变容二极管区域。两个或多个类型的电容器区域垂直布置在衬底上以形成电容器器件。这增加了电容器单元的电容，而不占用额外的布局面积。

9. 发明授权

US07061056B2 High fMAX deep submicron MOSFET 失效
标题翻译：高fMAX深亚微米MOSFET
公开(公告)号：US07061056B2
公开(公告)日：2006-06-13
申请号：US10623907
申请日：2003-07-18
申请人： Chao-Chieh Tsai , Shyh-Chyi Wong , Chung-Long Chang
发明人： Chao-Chieh Tsai , Shyh-Chyi Wong , Chung-Long Chang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28114 , H01L21/76819 , H01L21/76895 , H01L29/42376 , H01L29/4238 , H01L29/665
摘要： A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET. Whereby the width of the metal gate portion reduces Rg and increases the fMAX of the high fMAX deep submicron MOSFET.
摘要翻译：一种形成高密度亚微米级MOSFET的方法，包括以下步骤。提供其上形成有MOSFET的衬底。 MOSFET具有源极和漏极，并且在栅极上方包括硅化物部分。在衬底和MOSFET上形成第一ILD层。将第一ILD层平坦化以在栅电极上露出硅化物部分。金属栅极部分形成在平坦化的第一ILD层之上并且在栅电极上方的硅化物部分之上。金属栅极部分的宽度基本上大于栅电极上的硅化物部分的宽度。第二ILD层形成在金属栅极部分和第一ILD层上。通过与金属栅极部分接触的第二ILD层形成第一金属触点，并且通过接触漏极的第二和第一ILD层形成第二金属触点，从而形成高的最大深度亚微米MOSFET。由此金属栅极部分的宽度减小R＆lt;＆gt;并增加高的最大深亚微米MOSFET的最大最大值。

10. 发明申请

US20050082075A1 DEVICE AND METHOD FOR PROVIDING SHIELDING IN RADIO FREQUENCY INTEGRATED CIRCUITS TO REDUCE NOISE COUPLING 失效
标题翻译：在无线电频率集成电路中提供屏蔽以减少噪声耦合的装置和方法
公开(公告)号：US20050082075A1
公开(公告)日：2005-04-21
申请号：US10823874
申请日：2004-04-14
申请人： Wai-Yi Lien , Chung-Long Chang , Jyh-Chyurn Guo , John Chern
发明人： Wai-Yi Lien , Chung-Long Chang , Jyh-Chyurn Guo , John Chern
IPC分类号： H01L21/82 , H01L23/522 , H01L23/58 , H01L27/02 , H05K9/00
CPC分类号： H01L23/585 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed is a semiconductor radio frequency (RF) device having a shielding structure for minimizing coupling between RF passive components and conductive routing for active components. In one example, the device includes at least one shielding layer formed between the RF passive components and conductive routing. The shielding layer includes at least one opening. In another example, a second shielding layer may be used. The second shielding layer may also have an opening, and the openings in the first and second shielding layers may be offset from one another. The first and second shielding layers may be connected to each other through a guard ring, and may also be connected to a common voltage potential.
摘要翻译：公开了一种具有用于最小化RF无源部件之间的耦合的屏蔽结构和用于有源部件的导电布线的半导体射频（RF）装置。在一个示例中，该装置包括形成在RF无源部件和导电布线之间的至少一个屏蔽层。屏蔽层包括至少一个开口。在另一示例中，可以使用第二屏蔽层。第二屏蔽层也可以具有开口，并且第一和第二屏蔽层中的开口可以彼此偏移。第一和第二屏蔽层可以通过保护环彼此连接，并且还可以连接到公共电压电位。

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