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31. 发明申请

US20070085558A1 On-chip voltage regulator using feedback on process/product parameters 失效
标题翻译：片上电压调节器，使用过程/产品参数反馈
公开(公告)号：US20070085558A1
公开(公告)日：2007-04-19
申请号：US11638846
申请日：2006-12-13
申请人： Irfan Rahim , Peter McElheny , John Costello
发明人： Irfan Rahim , Peter McElheny , John Costello
IPC分类号： G01R31/26
CPC分类号： G11C5/147 , H03K19/177
摘要： The present invention optimizes the performance of integrated circuits by adjusting the circuit operating voltage using feedback on process/product parameters. To determine a desired value for the operating voltage of an integrated circuit, a preferred embodiment provides for on-wafer probing of one or more reference circuit structures to measure at least one electrical or operational parameter of the one or more reference circuit structures; determining an adjusted value for the operating voltage based on the measured parameter; and establishing the adjusted value as the desired value for the operating voltage. The reference circuit structures may comprise process control monitor structures or structures in other integrated circuits fabricated in the same production run. In an alternative embodiment, the one or more parameters are directly measured from the integrated circuit whose operating voltage is being adjusted
摘要翻译：本发明通过使用对过程/产品参数的反馈来调节电路工作电压来优化集成电路的性能。为了确定集成电路的工作电压的期望值，优选实施例提供一个或多个参考电路结构的片上探测，以测量一个或多个参考电路结构的至少一个电或操作参数; 基于所测量的参数确定所述工作电压的调整值; 并将调整后的值建立为工作电压的期望值。参考电路结构可以包括在相同生产运行中制造的其它集成电路中的过程控制监视器结构或结构。在替代实施例中，一个或多个参数是直接从其工作电压正被调整的集成电路测量的

32. 发明授权

US07142009B1 Adaptive power supply voltage regulation for programmable logic 有权
标题翻译：可编程逻辑的自适应电源电压调节
公开(公告)号：US07142009B1
公开(公告)日：2006-11-28
申请号：US10942692
申请日：2004-09-15
申请人： Jeffrey Watt , Irfan Rahim
发明人： Jeffrey Watt , Irfan Rahim
IPC分类号： H03K19/173 , G06F1/26
CPC分类号： H03K19/0008 , H03K19/177
摘要： Adaptive regulated power supply voltages are applied to programmable logic integrated circuits. Control circuitry in a programmable logic IC generates control signals that are transmitted to an external voltage regulator. The voltage regulator generates one or more power supply voltages in response to the control signals. The values of control signals determine the target values of the supply voltages. The control circuitry can adapt the power supply voltages to compensate for temperature and process variations on the IC. The power supply voltages can be programmed by a manufacturer or by a user to achieve desired target values. The control circuitry can also put a programmable logic IC into a sleep mode by dropping the high supply voltage to a low value to reduce power consumption during periods of low usage.
摘要翻译：自适应稳压电源电压被施加到可编程逻辑集成电路。可编程逻辑IC中的控制电路产生传输到外部电压调节器的控制信号。电压调节器响应于控制信号产生一个或多个电源电压。控制信号的值确定电源电压的目标值。控制电路可以调节电源电压以补偿IC上的温度和工艺变化。电源电压可以由制造商或用户编程以实现期望的目标值。控制电路还可以通过将高电源电压降低到低值来将可编程逻辑IC置于睡眠模式，以在低使用期间降低功耗。

33. 发明授权

US07129745B2 Apparatus and methods for adjusting performance of integrated circuits 有权
公开(公告)号：US07129745B2
公开(公告)日：2006-10-31
申请号：US10865402
申请日：2004-06-10
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： H03K19/173
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

34. 发明申请

US20060237784A1 Method and apparatus with varying gate oxide thickness 有权
标题翻译：具有不同栅极氧化物厚度的方法和装置
公开(公告)号：US20060237784A1
公开(公告)日：2006-10-26
申请号：US11114455
申请日：2005-04-25
申请人： Irfan Rahim , Yow-Juang Liu , Jeffrey Watt
发明人： Irfan Rahim , Yow-Juang Liu , Jeffrey Watt
IPC分类号： H01L29/76
CPC分类号： H01L27/0203 , H01L21/823857 , H01L27/0922 , H01L27/11807 , H01L27/11898 , Y10S257/903
摘要： An integrated circuit having an enhanced on-off swing for pass gate transistors is provided. The integrated circuit includes a core region that includes core transistors and pass gate transistors. The core transistors have a gate oxide associated with a first thickness, the pass transistors having a gate oxide associated with a thickness that is less than the first thickness. In one embodiment, the material used for the gate oxide of the pass gate transistors has a dielectric constant that is greater than four, while the material used for the gate oxide of the core transistors has a dielectric constant that is less than or equal to four. A method for manufacturing an integrated circuit is also provided.
摘要翻译：提供了一种具有用于通过栅极晶体管的增强的通断摆幅的集成电路。集成电路包括具有核心晶体管和栅极晶体管的核心区域。核心晶体管具有与第一厚度相关的栅极氧化物，所述通过晶体管具有与小于第一厚度的厚度相关联的栅极氧化物。在一个实施例中，用于栅极晶体管的栅极氧化物的材料具有大于4的介电常数，而用于核心晶体管的栅极氧化物的材料具有小于或等于4的介电常数。还提供了一种用于制造集成电路的方法。

35. 发明授权

US06963503B1 EEPROM with improved circuit performance and reduced cell size 失效
标题翻译： EEPROM具有改进的电路性能和减小的电池尺寸
公开(公告)号：US06963503B1
公开(公告)日：2005-11-08
申请号：US10618280
申请日：2003-07-11
申请人： Irfan Rahim , Veenu Shekhar
发明人： Irfan Rahim , Veenu Shekhar
IPC分类号： G11C16/04
CPC分类号： G11C16/0441 , G11C2216/10 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： An EEPROM cell with reduced cell size and improved circuit performance includes a high-voltage (HV) capacitor, a low-voltage (LV) read path, and an HV write path, wherein either the HV capacitor is placed between the LV read path and the HV write path or the HV write path is placed between the LV read path and the HV capacitor. The EEPROM cell also includes a native floating-gate (FG) transistor in the LV read path. Using a native FG transistor in the LV read path results in further reduction in the cell size and improved circuit performance of the EEPROM cell.
摘要翻译：具有减小的单元尺寸和改进的电路性能的EEPROM单元包括高压（HV）电容器，低电压（LV）读取路径和HV写入路径，其中HV电容器放置在LV读取路径和 HV写入路径或HV写入路径位于LV读取路径和HV电容器之间。 EEPROM单元还包括LV读取路径中的原生浮栅（FG）晶体管。在LV读取路径中使用本机FG晶体管导致EEPROM单元的单元尺寸的进一步减小和电路性能的提高。

36. 发明授权

US6069382A Non-volatile memory cell having a high coupling ratio 失效
标题翻译：具有高耦合比的非易失性存储单元
公开(公告)号：US6069382A
公开(公告)日：2000-05-30
申请号：US22222
申请日：1998-02-11
申请人： Irfan Rahim
发明人： Irfan Rahim
IPC分类号： H01L21/28 , H01L29/423 , H01L29/788
CPC分类号： H01L29/7883 , H01L21/28273 , H01L29/42324
摘要： A non-volatile memory cell includes a floating gate having a bottom surface in contact with a tunnel layer formed on the substrate, a top surface, and sidewall surfaces oriented along the bitline direction and along the wordline direction of the memory cell. A dielectric layer covers at least a portion of the top surface and covers at least a portion of the surfaces oriented along the bitline and wordline directions. A control gate overlaps the floating gate over substantially all of its surface area. A plurality of self-aligned sidewall spacers are provided, disposed against at least the dielectric layer and the control gate sidewalls. By overlapping the control gate over the floating gate, a greater surface area is made available for charge storage and/or for increasing the coupling ratio of the memory cell. This allows the width of wing structures to be decreased, while maintaining a high coupling ratio. This greater surface area, by increasing the coupling ratio of the memory cell, also allows the use of low programming and erase voltages. Charge retention and coupling are also increased by substantially overlapping or encapsulating the floating gate by the control gate, thus keeping it isolated from other structures, such as sidewall spacers.
摘要翻译：非易失性存储单元包括具有与形成在基板上的隧道层接触的底表面的浮动栅极，顶表面和沿着位线方向并沿着存储单元的字线方向定向的侧壁表面。电介质层覆盖顶表面的至少一部分并且覆盖沿着位线和字线方向定向的表面的至少一部分。控制栅极在其基本上所有的表面区域上与浮动栅极重叠。提供了多个自对准侧壁间隔物，其设置成抵靠至少介电层和控制栅极侧壁。通过在浮动栅极上重叠控制栅极，使更大的表面积可用于电荷存储和/或用于增加存储器单元的耦合比。这允许翼结构的宽度减小，同时保持高耦合比。通过增加存储单元的耦合比，该较大的表面积也允许使用低编程和擦除电压。电荷保持和耦合也通过由控制栅极基本上重叠或封装浮置栅极而增加，从而使其与诸如侧壁间隔物的其它结构隔离。

37. 发明授权

US09455715B2 Apparatus for improving reliability of electronic circuitry and associated methods 有权
标题翻译：用于提高电子电路和相关方法可靠性的装置
公开(公告)号：US09455715B2
公开(公告)日：2016-09-27
申请号：US13174599
申请日：2011-06-30
申请人： Bruce B. Pedersen , Irfan Rahim
发明人： Bruce B. Pedersen , Irfan Rahim
IPC分类号： H03K19/177 , H03K19/00 , H03K19/003
CPC分类号： H03K19/17752 , H03K19/003
摘要： In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus.
摘要翻译：在示例性实施例中，装置包括第一组电路元件和第二组电路元件。第一组电路元件用于装置的第一配置，并且第二组电路元件用于装置的第二配置。该设备的第一配置被切换到设备的第二配置，以便提高设备的可靠性。

38. 发明授权

US07800402B1 Look-up table overdrive circuits 有权
标题翻译：查找表超速电路
公开(公告)号：US07800402B1
公开(公告)日：2010-09-21
申请号：US11982865
申请日：2007-11-05
申请人： Irfan Rahim , Sriram Muthukumar , William Bradley Vest , Myron Wai Wong
发明人： Irfan Rahim , Sriram Muthukumar , William Bradley Vest , Myron Wai Wong
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/1778
摘要： A programmable logic device integrated circuit or other integrated circuit may have logic circuitry that produces data signals. The data signals may be routed to other logic circuits through interconnects. The interconnects may be programmable. A level recovery circuit may be used at the end of each interconnect line to strengthen the transmitted data signal. The level recovery circuit that is attached to a given interconnect line may produce true and complementary versions of the data signal that is on that interconnect line. Level shifting circuitry may be provided to boost the data signals on the interconnects. Each interconnect line may have a level shifter circuit that receives the true and complementary versions of a data signal and that produces corresponding boosted true and complementary versions of the data signal. The boosted signals may be provided to the control inputs of complementary-metal-oxide-semiconductor transistor pass gates in programmable look-up table circuitry.
摘要翻译：可编程逻辑器件集成电路或其他集成电路可以具有产生数据信号的逻辑电路。数据信号可以通过互连路由到其他逻辑电路。互连可以是可编程的。可以在每条互连线的末端使用电平恢复电路，以加强传输的数据信号。连接到给定互连线的电平恢复电路可以产生在该互连线上的数据信号的真实和互补版本。可以提供电平移位电路以升高互连上的数据信号。每个互连线可以具有电平移位器电路，其接收数据信号的真实和互补版本并且产生数据信号的相应增强的真实和互补版本。升压的信号可以提供给可编程查找表电路中的互补金属氧化物半导体晶体管栅极的控制输入。

39. 发明申请

US20080164936A1 Apparatus and Methods for Adjusting Performance of Programmable Logic Devices 审中-公开
标题翻译：用于调整可编程逻辑器件性能的装置和方法
公开(公告)号：US20080164936A1
公开(公告)日：2008-07-10
申请号：US12054382
申请日：2008-03-24
申请人： Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： G05F3/02 , H03K19/177
CPC分类号： H03K19/1731 , G06F17/5054 , H03K19/00369 , H03K2217/0018
摘要： A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).
摘要翻译：可编程逻辑器件（PLD）包括用于调整或设置一个或多个晶体管的体偏置的机构。 PLD包括体偏置发生器。体偏置发生器被配置为设置可编程逻辑器件内的一个或多个晶体管的体偏置。更具体地，体偏置发生器设置晶体管的体偏置，以便折衷晶体管的性能和功耗。

40. 发明授权

US07170308B1 On-chip voltage regulator using feedback on process/product parameters 有权
标题翻译：片上电压调节器，使用过程/产品参数反馈
公开(公告)号：US07170308B1
公开(公告)日：2007-01-30
申请号：US10628711
申请日：2003-07-28
申请人： Irfan Rahim , Peter McElheny , John Costello
发明人： Irfan Rahim , Peter McElheny , John Costello
IPC分类号： G01R31/00 , G01R31/28 , G05F1/00
CPC分类号： G11C5/147 , H03K19/177
摘要： The present invention optimizes the performance of integrated circuits by adjusting the circuit operating voltage using feedback on process/product parameters. To determine a desired value for the operating voltage of an integrated circuit, a preferred embodiment provides for on-wafer probing of one or more reference circuit structures to measure at least one electrical or operational parameter of the one or more reference circuit structures; determining an adjusted value for the operating voltage based on the measured parameter; and establishing the adjusted value as the desired value for the operating voltage. The reference circuit structures may comprise process control monitor structures or structures in other integrated circuits fabricated in the same production run. In an alternative embodiment, the one or more parameters are directly measured from the integrated circuit whose operating voltage is being adjusted.
摘要翻译：本发明通过使用对过程/产品参数的反馈来调节电路工作电压来优化集成电路的性能。为了确定集成电路的工作电压的期望值，优选实施例提供一个或多个参考电路结构的片上探测，以测量一个或多个参考电路结构的至少一个电或操作参数; 基于所测量的参数确定所述工作电压的调整值; 并将调整后的值建立为工作电压的期望值。参考电路结构可以包括在相同生产运行中制造的其它集成电路中的过程控制监视器结构或结构。在替代实施例中，一个或多个参数是直接从其工作电压正被调整的集成电路测量的。

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