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1. 发明授权

US06963503B1 EEPROM with improved circuit performance and reduced cell size 失效
标题翻译： EEPROM具有改进的电路性能和减小的电池尺寸
公开(公告)号：US06963503B1
公开(公告)日：2005-11-08
申请号：US10618280
申请日：2003-07-11
申请人： Irfan Rahim , Veenu Shekhar
发明人： Irfan Rahim , Veenu Shekhar
IPC分类号： G11C16/04
CPC分类号： G11C16/0441 , G11C2216/10 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： An EEPROM cell with reduced cell size and improved circuit performance includes a high-voltage (HV) capacitor, a low-voltage (LV) read path, and an HV write path, wherein either the HV capacitor is placed between the LV read path and the HV write path or the HV write path is placed between the LV read path and the HV capacitor. The EEPROM cell also includes a native floating-gate (FG) transistor in the LV read path. Using a native FG transistor in the LV read path results in further reduction in the cell size and improved circuit performance of the EEPROM cell.
摘要翻译：具有减小的单元尺寸和改进的电路性能的EEPROM单元包括高压（HV）电容器，低电压（LV）读取路径和HV写入路径，其中HV电容器放置在LV读取路径和 HV写入路径或HV写入路径位于LV读取路径和HV电容器之间。 EEPROM单元还包括LV读取路径中的原生浮栅（FG）晶体管。在LV读取路径中使用本机FG晶体管导致EEPROM单元的单元尺寸的进一步减小和电路性能的提高。

2. 发明授权

US08995175B1 Memory circuit with PMOS access transistors 有权
标题翻译：具有PMOS存取晶体管的存储电路
公开(公告)号：US08995175B1
公开(公告)日：2015-03-31
申请号：US13350575
申请日：2012-01-13
申请人： Jun Liu , Irfan Rahim , Yanzhong Xu , Andy L. Lee
发明人： Jun Liu , Irfan Rahim , Yanzhong Xu , Andy L. Lee
IPC分类号： G11C11/412 , G11C5/14
CPC分类号： G11C5/14 , G11C11/412 , G11C11/418
摘要： A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one implementation, the memory circuit further includes a bias clamp transistor coupled to the memory storage unit.
摘要翻译：描述了一种存储器电路，其包括存储器存储单元和耦合到存储器存储单元的存取晶体管，其中存取晶体管包括PMOS晶体管。在一个实现中，存储器电路还包括耦合到存储器存储单元的偏置钳位晶体管。

3. 发明授权

US08633731B1 Programmable integrated circuit with thin-oxide passgates 有权
标题翻译：可编程集成电路与薄氧化物通风门
公开(公告)号：US08633731B1
公开(公告)日：2014-01-21
申请号：US13206401
申请日：2011-08-09
申请人： Irfan Rahim , Mao Du , Jeffrey Xiaoqi Tung , Jun Liu , Qi Xiang
发明人： Irfan Rahim , Mao Du , Jeffrey Xiaoqi Tung , Jun Liu , Qi Xiang
IPC分类号： G06F7/38
CPC分类号： H03K19/1733 , G11C8/16 , G11C11/419
摘要： Integrated circuits such as programmable integrated circuits may have configuration random-access memory elements. The configuration random-access memory elements may be loaded with configuration data to customize programmable circuitry on the integrated circuits. Each memory element may have a bistable element that is powered using a positive power supply voltage and a negative power supply voltage. Programmable transistors in the programmable circuitry may have gates coupled to outputs of the bistable elements. The programmable transistors may have gate insulators that are thinner than gate insulators in the transistors of the bistable elements and may have threshold voltages of about zero volts. During operation, some of the configuration random-access memory elements may supply negative voltages to their associated programmable transistors so that the programmable transistors are provided with gate-source voltages of less than zero volts.
摘要翻译：诸如可编程集成电路的集成电路可以具有配置随机存取存储器元件。配置随机存取存储器元件可以被加载配置数据以定制集成电路上的可编程电路。每个存储元件可以具有使用正电源电压和负电源电压供电的双稳态元件。可编程电路中的可编程晶体管可以具有耦合到双稳态元件的输出的栅极。可编程晶体管可以具有比双稳态元件的晶体管中的栅极绝缘体更薄的栅极绝缘体，并且可以具有约零伏特的阈值电压。在操作期间，一些配置随机存取存储器元件可以向其相关联的可编程晶体管提供负电压，使得可编程晶体管具有小于零伏的栅极 - 源极电压。

4. 发明授权

US08611137B2 Memory elements with relay devices 有权
标题翻译：具有中继设备的存储器元件
公开(公告)号：US08611137B2
公开(公告)日：2013-12-17
申请号：US13304226
申请日：2011-11-23
申请人： Lin-Shih Liu , Mark T. Chan , Yanzhong Xu , Irfan Rahim , Jeffrey T. Watt
发明人： Lin-Shih Liu , Mark T. Chan , Yanzhong Xu , Irfan Rahim , Jeffrey T. Watt
IPC分类号： G11C11/00
CPC分类号： G11C11/52 , B82Y10/00 , G11C13/025 , G11C23/00 , H01H1/0094 , H01H1/20 , H01H59/0009 , H01L27/101 , H01L27/11
摘要： Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.
摘要翻译：提供具有存储元件的集成电路。集成电路可以包括形成在具有互补金属氧化物半导体（CMOS）器件的第一部分中的逻辑电路，并且可以包括形成在具有纳米机电（NEM）器件的第二部分中的存储器元件和相关联的存储器电路的至少一部分，中继设备 NEM和CMOS器件可以通过介电堆叠中的通孔互连。第一和第二部分中的装置可以接收相应的电源电压。在一个合适的布置中，存储器元件可以包括提供非易失性存储特性和软错误失真（SEU）抗扰性的两个继电器开关。在另一种合适的布置中，存储元件可以包括第一和第二交叉耦合反相电路。第一反相电路可以包括继电器开关，而第二反相电路仅包括CMOS晶体管。以这种方式配置的存储器元件可用于提供易失性存储特性和SEU抗扰度。

5. 发明授权

US08030962B2 Configuration random access memory 有权
标题翻译：配置随机存取存储器
公开(公告)号：US08030962B2
公开(公告)日：2011-10-04
申请号：US12868575
申请日：2010-08-25
申请人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
发明人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译：提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。每个存储器元件具有存储该存储器元件的数据的电容器。一对交叉耦合的反相器连接到电容器。逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。每个配置随机存取存储器元件可以具有透明晶体管。电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。逆变器可以用升高的电源电压供电。

6. 发明授权

US07902611B1 Integrated circuit well isolation structures 有权
标题翻译：集成电路阱隔离结构
公开(公告)号：US07902611B1
公开(公告)日：2011-03-08
申请号：US11998016
申请日：2007-11-27
申请人： Irfan Rahim , Bradley Jensen , Peter J. McElheny
发明人： Irfan Rahim , Bradley Jensen , Peter J. McElheny
IPC分类号： H01L21/70 , H01L23/52 , H01L29/00
CPC分类号： H01L27/0928 , H01L21/76224 , H01L21/765 , H01L21/823878 , H01L21/823892
摘要： An integrated circuit is provided with transistor body regions that may be independently biased. Some of the bodies may be forward body biased to lower threshold voltages and increase transistor switching speed. Some of the bodies may be reverse body biased to increase threshold voltages and decrease leakage current. The integrated circuit may be formed on a silicon substrate. Body bias isolation structures may be formed in the silicon substrate to isolate the bodies from each other. Body bias isolation structures may be formed from shallow trench isolation trenches. Doped regions may be formed at the bottom of the trenches using ion implantation. Oxide may be used to fill the trenches above the doped region. A deep well may be formed under the body regions. The deep well may contact the doped regions that are formed at the bottom of the trenches.
摘要翻译：集成电路设置有可独立偏置的晶体管本体区域。一些物体可能被向前偏置，以降低阈值电压并增加晶体管切换速度。一些物体可能被反向体偏置以增加阈值电压并减小漏电流。集成电路可以形成在硅衬底上。可以在硅衬底中形成体偏置隔离结构以将体彼此隔离。体偏置隔离结构可以由浅沟槽隔离沟槽形成。可以使用离子注入在沟槽的底部形成掺杂区域。氧化物可用于填充掺杂区域上方的沟槽。可以在身体区域下方形成深井。深阱可以接触形成在沟槽底部的掺杂区域。

7. 发明授权

US07639033B2 On-chip voltage regulator using feedback on process/product parameters 失效
标题翻译：片上电压调节器，使用过程/产品参数反馈
公开(公告)号：US07639033B2
公开(公告)日：2009-12-29
申请号：US11638846
申请日：2006-12-13
申请人： Irfan Rahim , Peter McElheny , John Costello
发明人： Irfan Rahim , Peter McElheny , John Costello
IPC分类号： G01R31/00 , G01R31/28
CPC分类号： G11C5/147 , H03K19/177
摘要： The present invention optimizes the performance of integrated circuits by adjusting the circuit operating voltage using feedback on process/product parameters. To determine a desired value for the operating voltage of an integrated circuit, a preferred embodiment provides for on-wafer probing of one or more reference circuit structures to measure at least one electrical or operational parameter of the one or more reference circuit structures; determining an adjusted value for the operating voltage based on the measured parameter; and establishing the adjusted value as the desired value for the operating voltage. The reference circuit structures may comprise process control monitor structures or structures in other integrated circuits fabricated in the same production run. In an alternative embodiment, the one or more parameters are directly measured from the integrated circuit whose operating voltage is being adjusted.
摘要翻译：本发明通过使用对过程/产品参数的反馈来调节电路工作电压来优化集成电路的性能。为了确定集成电路的工作电压的期望值，优选实施例提供一个或多个参考电路结构的片上探测，以测量一个或多个参考电路结构的至少一个电或操作参数; 基于所测量的参数确定所述工作电压的调整值; 并将调整后的值建立为工作电压的期望值。参考电路结构可以包括在相同生产运行中制造的其它集成电路中的过程控制监视器结构或结构。在替代实施例中，一个或多个参数是直接从其工作电压正被调整的集成电路测量的。

8. 发明申请

US20090289696A1 Apparatus and Methods for Adjusting Performance of Integrated Circuits 有权
标题翻译：用于调整集成电路性能的装置和方法
公开(公告)号：US20090289696A1
公开(公告)日：2009-11-26
申请号：US12534101
申请日：2009-07-31
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： H03K3/01 , G06F17/50 , H03K19/177
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
摘要翻译：可编程逻辑器件（PLD）包括延迟电路和体偏置发生器。延迟电路具有被配置为表示PLD中的用户电路实现的延迟的延迟。体偏置发生器被配置为调整用户电路内的晶体管的体偏置。体偏置发生器响应于从延迟电路的信号传播延迟导出的电平来调节晶体管的体偏置。

9. 发明授权

US07573317B2 Apparatus and methods for adjusting performance of integrated circuits 有权
标题翻译：用于调整集成电路性能的装置和方法
公开(公告)号：US07573317B2
公开(公告)日：2009-08-11
申请号：US11535065
申请日：2006-09-26
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： H03K3/01
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
摘要翻译：可编程逻辑器件（PLD）包括延迟电路和体偏置发生器。延迟电路具有被配置为表示PLD中的用户电路实现的延迟的延迟。体偏置发生器被配置为调整用户电路内的晶体管的体偏置。体偏置发生器响应于从延迟电路的信号传播延迟导出的电平来调节晶体管的体偏置。

10. 发明授权

US07465971B2 Integrated circuit structures for increasing resistance to single event upset 有权
公开(公告)号：US07465971B2
公开(公告)日：2008-12-16
申请号：US11951122
申请日：2007-12-05
申请人： Lakhbeer S. Sidhu , Irfan Rahim , Jeffrey Watt , John Turner
发明人： Lakhbeer S. Sidhu , Irfan Rahim , Jeffrey Watt , John Turner
IPC分类号： H01L29/94
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/11807
摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

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