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31. 发明申请

US20210200464A1 MEMORY DEVICE INTERFACE AND METHOD 有权
公开(公告)号：US20210200464A1
公开(公告)日：2021-07-01
申请号：US17136728
申请日：2020-12-29
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G06F3/06
摘要： Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.

32. 发明授权

US09214449B2 Reconfigurable connections for stacked semiconductor devices 有权
标题翻译：层叠半导体器件的可重构连接
公开(公告)号：US09214449B2
公开(公告)日：2015-12-15
申请号：US13367026
申请日：2012-02-06
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G01R31/26 , H01L25/065 , G11C5/02 , G11C5/06 , G11C29/02 , G11C29/00 , G11C5/04 , G11C29/32
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C5/06 , G11C29/02 , G11C29/022 , G11C29/70 , G11C2029/3202 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/1531 , H01L2924/00
摘要： Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.
摘要翻译：一些实施例包括包括布置在堆叠中的半导体裸片的装置，系统和方法，被配置为提供骰子之间的通信的多个连接，穿过至少一个骰子的连接的至少一部分，以及被配置为检查连接中的缺陷并修复连接的缺陷。

33. 发明授权

US08712249B2 Optical interconnect in high-speed memory systems 有权
标题翻译：高速存储器系统中的光互连
公开(公告)号：US08712249B2
公开(公告)日：2014-04-29
申请号：US13080376
申请日：2011-04-05
申请人： Russel J. Baker , Brent Keeth
发明人： Russel J. Baker , Brent Keeth
IPC分类号： H04B10/00
CPC分类号： G11C11/4093 , G06F13/16 , G06F13/1668 , G06F13/287 , G06F13/4234 , G11C11/42 , H04B10/802 , H04L12/40013 , H04Q11/0071 , Y02D10/14 , Y02D10/151
摘要： A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.
摘要翻译：公开了一种用于实现控制器和存储器件之间的电气隔离的光学链路。光链路增加了电互连的抗噪声能力，并且允许存储器件被放置在距离处理器更远的位置，而不需要耗电的I / O缓冲器。

34. 发明申请

US20120246434A1 SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE 有权
标题翻译：基于命令信号和操作状态解码命令的系统和方法
公开(公告)号：US20120246434A1
公开(公告)日：2012-09-27
申请号：US13489246
申请日：2012-06-05
申请人： Jeffrey W. Janzen , Brent Keeth , Jeffrey P. Wright , James S. Cullum
发明人： Jeffrey W. Janzen , Brent Keeth , Jeffrey P. Wright , James S. Cullum
IPC分类号： G06F12/00
CPC分类号： G11C11/4096 , G11C7/1072 , G11C11/40611 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.
摘要翻译：一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产生内部控制信号，以根据命令信号和操作状态执行操作。命令信号的相同组合可以根据操作状态请求不同的命令。当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令州。

35. 发明申请

US20120133387A1 RECONFIGURABLE CONNECTIONS FOR STACKED SEMICONDUCTOR DEVICES 有权
标题翻译：堆叠式半导体器件的可重构连接
公开(公告)号：US20120133387A1
公开(公告)日：2012-05-31
申请号：US13367026
申请日：2012-02-06
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G01R31/26
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C5/06 , G11C29/02 , G11C29/022 , G11C29/70 , G11C2029/3202 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/1531 , H01L2924/00
摘要： Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.
摘要翻译：一些实施例包括包括布置在堆叠中的半导体裸片的装置，系统和方法，被配置为提供骰子之间的通信的多个连接，穿过至少一个骰子的连接的至少一部分，以及被配置为检查连接中的缺陷并修复连接中的缺陷。

36. 发明授权

US07816934B2 Reconfigurable connections for stacked semiconductor devices 有权
标题翻译：层叠半导体器件的可重构连接
公开(公告)号：US07816934B2
公开(公告)日：2010-10-19
申请号：US11873118
申请日：2007-10-16
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G01R31/02
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C5/06 , G11C29/02 , G11C29/022 , G11C29/70 , G11C2029/3202 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/1531 , H01L2924/00
摘要： Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.
摘要翻译：一些实施例包括包括布置在堆叠中的半导体裸片的装置，系统和方法，被配置为提供骰子之间的通信的多个连接，穿过至少一个骰子的连接的至少一部分，以及被配置为检查连接中的缺陷并修复连接中的缺陷。

37. 发明授权

US07549033B2 Dual edge command 有权
标题翻译：双边命令
公开(公告)号：US07549033B2
公开(公告)日：2009-06-16
申请号：US11495418
申请日：2006-07-28
申请人： Joo S. Choi , Troy A. Manning , Brent Keeth
发明人： Joo S. Choi , Troy A. Manning , Brent Keeth
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C11/4076 , G06F12/0207 , G06F13/1668 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C11/408 , G11C11/409
摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.
摘要翻译：一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

38. 发明申请

US20090141571A1 Method and Apparatus for Initialization of Read Latency Tracking Circuit in High-Speed DRAM 有权
标题翻译：用于在高速DRAM中初始化读延迟跟踪电路的方法和装置
公开(公告)号：US20090141571A1
公开(公告)日：2009-06-04
申请号：US12329779
申请日：2008-12-08
申请人： James Brian Johnson , Brent Keeth , Feng Dan Lin
发明人： James Brian Johnson , Brent Keeth , Feng Dan Lin
IPC分类号： G11C7/00 , G11C8/18 , G11C8/00
CPC分类号： G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4072 , G11C11/4076 , G11C2207/2254 , H03L7/0812 , H03L7/095
摘要： A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command. The held value of the second counter is compared to a running count of the first counter; and data is output from the memory device with the read clock signal in response to the comparing.
摘要翻译：控制来自存储器件的数据输出的方法包括从外部时钟信号导出读时钟和用于操作存储单元阵列的控制时钟，读时钟和控制时钟均由时钟脉冲组成。值被预加载到位于读时钟域中的第一计数器中的一个或两者，位于控制时钟域中的第二计数器，使得两个计数器之间的启动计数的差值等于列地址选通延迟（L）减去同步（SP）开销。产生起始信号，用于开始产生第一计数器中的读取时钟脉冲的运行计数。启动信号到第二计数器的输入被延迟，以延迟启动控制时钟脉冲的运行计数。响应于读取命令来保持第二计数器的值。将第二计数器的保持值与第一计数器的运行计数进行比较; 并且响应于比较，从存储器件输出具有读时钟信号的数据。

39. 发明授权

US07480203B2 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM 有权
公开(公告)号：US07480203B2
公开(公告)日：2009-01-20
申请号：US12072109
申请日：2008-02-22
申请人： James Brian Johnson , Brent Keeth , Feng (Dan) Lin
发明人： James Brian Johnson , Brent Keeth , Feng (Dan) Lin
IPC分类号： G11C8/00 , H03L7/06
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2254 , H03L7/0812 , H03L7/095
摘要： A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock. The input of the start signal to a second counter is delayed to delay the initiation of a running count of the control clock pulses. The delay, which may be expressed as an integer number of clock cycles, may be equal to an input/output delay of the memory device. The method may be modified by inputting the start signal to an offset counter before initiating the production of the running count of the read clock pulses in the first counter. The offset counter may be loaded with a value equal to a programmed latency less a synchronization overhead. Once the running counts are initiated, each time a read command is received, a then current value of the running count of control clock pulses from the second counter is latched or held. The held value is compared to the running count of read clock pulses from the first counter, with the read clock signal being used to output data in response to the comparison. Apparatus for implementing the disclosed methods are also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

40. 发明申请

US20080089158A1 Memory device and method having data path with multiple prefetch I/O configurations 失效
标题翻译：具有多个预取I / O配置的数据路径的存储器件和方法
公开(公告)号：US20080089158A1
公开(公告)日：2008-04-17
申请号：US11999383
申请日：2007-12-04
申请人： Brent Keeth , Brian Johnson , Troy Manning
发明人： Brent Keeth , Brian Johnson , Troy Manning
IPC分类号： G11C7/00
CPC分类号： G11C7/1072 , G11C7/1006 , G11C7/1018 , G11C7/1027 , G11C7/1045 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.
摘要翻译：存储器件可以在高模式或低速模式下操作。在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线终端。在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个巴士总站。

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