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31. 发明授权

US06667641B1 Programmable phase shift circuitry 失效
公开(公告)号：US06667641B1
公开(公告)日：2003-12-23
申请号：US10056787
申请日：2002-01-23
申请人： Bonnie I. Wang , Joseph Huang , Chiakang Sung , Xiaobao Wang , In Whan Kim , Wayne Yeung , Khai Nguyen
发明人： Bonnie I. Wang , Joseph Huang , Chiakang Sung , Xiaobao Wang , In Whan Kim , Wayne Yeung , Khai Nguyen
IPC分类号： H03L708
CPC分类号： H03K19/1774 , H03K23/665 , H03K2005/00045 , H03L7/081 , H03L7/0891 , H03L7/0996 , H03L7/0997 , H03L7/183
摘要： A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

32. 发明授权

US06642758B1 Voltage, temperature, and process independent programmable phase shift for PLL 有权
标题翻译： PLL的电压，温度和过程独立的可编程相移
公开(公告)号：US06642758B1
公开(公告)日：2003-11-04
申请号：US09731473
申请日：2000-12-05
申请人： Bonnie I. Wang , Joseph Huang , Chiakang Sung , Xiaobao Wang , In Whan Kim , Wayne Yeung , Khai Nguyen
发明人： Bonnie I. Wang , Joseph Huang , Chiakang Sung , Xiaobao Wang , In Whan Kim , Wayne Yeung , Khai Nguyen
IPC分类号： H03L7095
CPC分类号： H03L7/0891 , H03F1/301 , H03H11/245 , H03K19/1774 , H03K23/665 , H03K2005/00045 , H03L7/081 , H03L7/089 , H03L7/0996 , H03L7/0997 , H03L7/18 , H03L7/183
摘要： A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.
摘要翻译：电路提供可编程相移特征，其中相移可由用户可编程地选择。该电路可以并入可编程逻辑器件（PLD）或现场可编程门阵列（FPGA）中，以提供额外的可编程特性。可编程相移电路可以在锁相环（PLL）或延迟锁定环（DLL）电路内实现。在实现中，使用两个可编程计数器来实现可编程相移电路。

33. 发明授权

US06617884B2 Fast locking phase frequency detector 有权
公开(公告)号：US06617884B2
公开(公告)日：2003-09-09
申请号：US10160355
申请日：2002-05-28
申请人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Khai Nguyen , Wayne Yeung , In Whan Kim
发明人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Khai Nguyen , Wayne Yeung , In Whan Kim
IPC分类号： H03D1300
CPC分类号： H03K19/1774 , H03K2005/00045 , H03L7/081 , H03L7/0891 , H03L7/0996 , H03L7/0997 , H03L7/183
摘要： A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

34. 发明授权

US06448820B1 Fast locking phase frequency detector 有权
公开(公告)号：US06448820B1
公开(公告)日：2002-09-10
申请号：US09432442
申请日：1999-11-02
申请人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Khai Nguyen , Wayne Yeung , In Whan Kim
发明人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Khai Nguyen , Wayne Yeung , In Whan Kim
IPC分类号： H03D1300
CPC分类号： H03K19/1774 , H03K2005/00045 , H03L7/081 , H03L7/0891 , H03L7/0996 , H03L7/0997 , H03L7/183
摘要： A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

35. 发明授权

US06433579B1 Programmable logic integrated circuit devices with differential signaling capabilities 有权
标题翻译：具有差分信号功能的可编程逻辑集成电路器件
公开(公告)号：US06433579B1
公开(公告)日：2002-08-13
申请号：US09863143
申请日：2001-05-22
申请人： Bonnie I. Wang , Chiakang Sung , Yan Chong , Philip Pan , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopinath Rangan
发明人： Bonnie I. Wang , Chiakang Sung , Yan Chong , Philip Pan , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopinath Rangan
IPC分类号： H03K19177
CPC分类号： H03K19/17744 , H03K19/018521 , H03K19/1778 , H03K19/17784 , H03K19/17792
摘要： A programmable logic device is equipped for various differential signaling schemes by providing a differential output buffer on the device that can be configured according to the needs of the particular differential signaling schemes that may be used. The buffer includes a differential output driver, an adjustable current limiting circuit between the supply voltage and the differential output driver, and an adjustable current limiting circuit between the differential output driver and ground. By selectively adjusting the two current limiting circuits, the output impedance and current, as well as the common mode output voltage and the differential output voltage can be controlled.
摘要翻译：通过在设备上提供可根据可能使用的特定差分信令方案的需要进行配置的差分输出缓冲器，为各种差分信令方案配备了可编程逻辑器件。缓冲器包括差分输出驱动器，电源电压和差分输出驱动器之间的可调节限流电路，以及差分输出驱动器和地之间的可调电流限制电路。通过选择性地调节两个限流电路，可以控制输出阻抗和电流，以及共模输出电压和差分输出电压。

36. 发明授权

US06262595B1 High-speed programmable interconnect 失效
公开(公告)号：US06262595B1
公开(公告)日：2001-07-17
申请号：US09094356
申请日：1998-06-09
申请人： Joseph Huang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen , Xiaobao Wang , Richard G. Cliff
发明人： Joseph Huang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen , Xiaobao Wang , Richard G. Cliff
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , G01R31/318555 , G06F11/2273 , H03K19/17792
摘要： An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.

37. 发明授权

US07590879B1 Clock edge de-skew 有权
标题翻译：时钟边缘去偏移
公开(公告)号：US07590879B1
公开(公告)日：2009-09-15
申请号：US11043524
申请日：2005-01-24
申请人： Henry Kim , Bonnie I. Wang , ChiaKang Sung , Joseph Huang
发明人： Henry Kim , Bonnie I. Wang , ChiaKang Sung , Joseph Huang
IPC分类号： G06F1/12 , G06F9/00 , G06F13/42
CPC分类号： G06F13/4243
摘要： Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal such that a clock signal is centered relative to the data. A further embodiment of the present invention recovers a double-data rate signal using two flip-flops, one clocked by clock rising edges, the other clocked by clock falling edges. An additional delay element is inserted in front of one or both flip-flop clock inputs. If two additional delay elements are used, they are independently adjustable such that each edge can be independently adjusted for improved data recovery.
摘要翻译：用于对时钟信号的上升沿和下降沿进行偏移的电路，方法和装置。本发明的一个实施例利用数据路径中的延迟元件来调整数据信号，使得时钟信号相对于数据居中。本发明的另一实施例使用两个触发器来恢复双数据速率信号，其中一个触发器由时钟上升沿计时，另一个由时钟下降沿计时。在一个或两个触发器时钟输入的前面插入一个附加的延迟元件。如果使用两个额外的延迟元件，则它们可独立调节，以便可以独立调整每个边沿以改善数据恢复。

38. 发明授权

US07324405B1 DQS postamble filtering 有权
标题翻译： DQS后同步码过滤
公开(公告)号：US07324405B1
公开(公告)日：2008-01-29
申请号：US11368369
申请日：2006-03-03
申请人： Sanjay K. Charagulla , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Yan Chong
发明人： Sanjay K. Charagulla , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Yan Chong
IPC分类号： G11C8/00
CPC分类号： H03K5/135 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , H03M9/00
摘要： Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.
摘要翻译：用于在高速数据接口处过滤信号的电路，方法和装置。一个示例性实施例被特别地配置为在由双数据速率存储器接口接收的数据突发结束时对时钟信号进行滤波。时钟输入端口与输入单元连接或断开。当接收到数据脉冲串时，时钟输入端口连接到输入单元。当数据突发结束时，时钟输入端口与输入单元断开连接。在具体实施例中，接收到指示数据脉冲串即将开始并且时钟输入端口连接到输入单元的信号。该信号随后改变指示正在接收最后一个数据位的状态。当接收到与最后一个数据位相对应的最后一个时钟沿时，时钟输入端口与输入单元断开。

39. 发明授权

US07200769B1 Self-compensating delay chain for multiple-date-rate interfaces 有权
标题翻译：多速率接口的自补偿延迟链
公开(公告)号：US07200769B1
公开(公告)日：2007-04-03
申请号：US10037861
申请日：2002-01-02
申请人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
发明人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
IPC分类号： G06F1/04
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C2207/108 , H03L7/0805 , H03L7/0814 , H03L7/091
摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.
摘要翻译：用于延迟多数据速率接口的时钟信号的方法和装置。一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

40. 发明授权

US06373278B1 LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device 有权
标题翻译： LVDS接口结合了可编程逻辑器件中的锁相环电路
公开(公告)号：US06373278B1
公开(公告)日：2002-04-16
申请号：US09758674
申请日：2001-01-11
申请人： Chiakang Sung , Bonnie I. Wang , Richard G. Cliff
发明人： Chiakang Sung , Bonnie I. Wang , Richard G. Cliff
IPC分类号： H03K19173
CPC分类号： H03L7/18 , H03L7/07 , H03L7/0891
摘要： An LVDS interface for a programmable logic device uses phase-locked loop (“PLL”) circuits to provide data clocks for data input and output. The PLL clocks are highly accurate and each includes a multiply-by-W counter so that a multiplied and an unmultiplied clock are available. The multiplied clock is used to clock data into or out of a shift register chain serially. The unmultiplied clock is used to load or read the registers in the shift register chain in parallel. Providing both the multiplied and unmultiplied clocks from a single PLL assures that the clocks are in proper phase relationship so that the serial inputting or outputting, and the parallel loading or unloading, are properly synchronized.
摘要翻译：用于可编程逻辑器件的LVDS接口使用锁相环（“PLL”）电路为数据输入和输出提供数据时钟。 PLL时钟是高精度的，每个包括一个乘以W的计数器，以便可以使用倍增和非乘法时钟。倍增时钟用于将数据串行时移到或移出移位寄存器链。非乘法时钟用于并行加载或读取移位寄存器链中的寄存器。从单个PLL提供相乘和非乘法时钟确保时钟处于正确的相位关系，以便串行输入或输出以及并行加载或卸载被正确同步。

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