专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07435659B2 Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process 有权
标题翻译：用于制造具有使用N型掺杂剂形成的取向特征和湿式氧化处理的半导体器件的方法
公开(公告)号：US07435659B2
公开(公告)日：2008-10-14
申请号：US11068117
申请日：2005-02-28
申请人： Binghua Hu , Sameer P. Pendharkar , Bill A. Wofford , Joseph M. Ramirez
发明人： Binghua Hu , Sameer P. Pendharkar , Bill A. Wofford , Joseph M. Ramirez
IPC分类号： H01L21/76
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/2652 , H01L21/823493 , H01L21/8249 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further include oxidizing the substrate using a wet oxidation process, the wet oxidation process and n-type dopant causing a ratio of oxidation of the implanted region to the unimplanted region to be 2:1 or greater, and then removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region.
摘要翻译：本发明提供一种具有对准特征的半导体器件的制造方法。除了其他步骤之外，制造半导体器件的方法可以包括将n型掺杂剂注入衬底中，从而在衬底中形成注入区域和未被注入的区域。该方法可以进一步包括使用湿式氧化法，湿法氧化法和n型掺杂剂使得注入区域与未被注入的区域的氧化比例为2:1或更大，然后除去氧化部分从而在植入区域附近留下对准特征。

32. 发明申请

US20080085569A1 METHOD OF USING ELECTRICAL TEST STRUCTURE FOR SEMICONDUCTOR TRENCH DEPTH MONITOR 有权
标题翻译：使用电子测试结构的半导体TRENCH深度监测器的方法
公开(公告)号：US20080085569A1
公开(公告)日：2008-04-10
申请号：US11531103
申请日：2006-09-12
申请人： Qingfeng Wang , Sameer P. Pendharkar , Binghua Hu
发明人： Qingfeng Wang , Sameer P. Pendharkar , Binghua Hu
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L29/0649 , H01L29/8605
摘要： Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.
摘要翻译：实施例提供了用于电监测半导体器件中的沟槽深度的方法和装置。为了电测量沟槽深度，可以在半导体衬底上的深阱区域中形成夹持电阻器。然后可以在夹持电阻器中形成沟槽。沟槽深度可以通过夹持电阻器的电气测试来确定。所公开的方法和装置可以跨晶片提供统计数据分析，并且可以在作为过程监视器的生产划线中实施。所公开的方法也可用于确定LDMOS晶体管的器件性能。 LDMOS晶体管的导通电阻（Rdson）可以与沟槽深度的电测量相关。

33. 发明申请

US20070048952A1 METHOD TO MANUFACTURE LDMOS TRANSISTORS WITH IMPROVED THRESHOLD VOLTAGE CONTROL 有权
标题翻译：用改进的阈值电压控制制造LDMOS晶体管的方法
公开(公告)号：US20070048952A1
公开(公告)日：2007-03-01
申请号：US11552198
申请日：2006-10-24
申请人： Binghua Hu , Howard Lee , Henry Edwards , John Lin , Vladimir Bolkhovsky
发明人： Binghua Hu , Howard Lee , Henry Edwards , John Lin , Vladimir Bolkhovsky
IPC分类号： H01L21/336
CPC分类号： H01L21/266 , H01L21/2652 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).
摘要翻译：在外延层（20）中形成双扩散区域（65），（75），（85）。通过在硬烘烤过程之前首先将诸如硼的光注入物质在光致抗蚀剂层中的开口注入，形成双扩散区域。在硬烘烤过程之后，可以将诸如砷的重植入物种植入外延层中。在后续处理（如LOCOS形成）中形成双扩散区。在外延层（20）上形成介电层（120），并且在电介质层（120）之上形成栅极结构（130），（135）。

34. 发明授权

US08497565B2 Multiple electrode layer backend stacked capacitor 有权
标题翻译：多电极层后端层叠电容器
公开(公告)号：US08497565B2
公开(公告)日：2013-07-30
申请号：US13043066
申请日：2011-03-08
申请人： Byron Lovell Willaims , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
发明人： Byron Lovell Willaims , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
IPC分类号： H01L21/02
CPC分类号： H01L28/91
摘要： In a disclosed embodiment, a stacked capacitor (100) has bottom, middle and top metal electrode layers (141A, 141B, 141C) interleaved with dielectric layers (142A, 142B) conformally disposed within holes (140A, 140B, 140C) in a protective overcoat or backend dielectric layer (110) over a top metal layer (115) of an integrated circuit (105). A top electrode (155) contacts the top metal electrode layer (141C). A bottom electrode (150) electrically couples an isolated part of the top metal electrode layer (141C) through a bottom electrode via (165A) to a first contact node (135A) in the top metal layer (115) which is in contact with the bottom metal electrode layer (141A). A middle electrode (160) electrically couples a part of the middle metal electrode layer (141B) not covered by the top metal layer (115) through a middle electrode via (165B) to a second contact node (135B) in the top metal electrode layer (115). The sidewalls of the top and middle electrode vias (165A, 165B) are lined with insulating material to electrically isolate the metal electrode layer ends.
摘要翻译：在公开的实施例中，叠层电容器（100）具有与保护性地设置在保护孔（140A，140B，140C）内的电介质层（142A，142B）交错的底部，中间和顶部金属电极层（141A，141B，141C）外部涂层或后端电介质层（110）覆盖在集成电路（105）的顶部金属层（115）上。顶部电极（155）接触顶部金属电极层（141C）。底部电极（150）通过（165A）将顶部金属电极层（141C）的隔离部分电耦合到顶部金属层（115）中与第一接触节点（135A）接触的第一接触节点（135A）底部金属电极层（141A）。中间电极（160）将未被顶部金属层（115）覆盖的中间金属电极层（141B）的一部分通过中间电极（165B）电耦合到顶部金属电极中的第二接触节点（135B）层（115）。顶部和中间电极通孔（165A，165B）的侧壁衬有绝缘材料以电绝缘金属电极层端部。

35. 发明授权

US08264038B2 Buried floating layer structure for improved breakdown 有权
标题翻译：埋地浮层结构，可改善故障
公开(公告)号：US08264038B2
公开(公告)日：2012-09-11
申请号：US12537326
申请日：2009-08-07
申请人： Sameer P. Pendharkar , Binghua Hu , Xinfen Chen
发明人： Sameer P. Pendharkar , Binghua Hu , Xinfen Chen
IPC分类号： H01L29/06 , H01L29/78 , H01L29/73 , H01L27/092 , H01L21/761
CPC分类号： H01L21/761 , H01L21/823892 , H01L29/0623 , H01L29/0653 , H01L29/086 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/7322 , H01L29/7816 , H01L29/7833
摘要： A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.
摘要翻译：公开了一种掩埋层结构，其包括与连接到IC中的组件的相同导电类型的深阱连接的高电压埋层相邻的浮置掩埋层结构。浮置掩埋层结构围绕高压掩埋层并且延伸埋层的耗尽区以减小掩埋层的侧边缘处的峰值电场。当浮动掩埋层结构的尺寸和间距被优化时，连接到掩埋层的阱可被偏压到100伏而不会破坏。添加围绕第一浮动掩埋层结构的第二浮动掩埋层结构允许埋入层的操作高达140伏。具有浮动掩埋层结构的掩埋层结构可以并入DEPMOS晶体管，LDMOS晶体管，埋地集电极npn双极晶体管和隔离CMOS电路中。

36. 发明申请

US20110156209A1 MULTIPLE ELECTRODE LAYER BACKEND STACKED CAPACITOR 有权
标题翻译：多层电极层背板堆叠电容
公开(公告)号：US20110156209A1
公开(公告)日：2011-06-30
申请号：US13043066
申请日：2011-03-08
申请人： Byron Lovell Williams , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
发明人： Byron Lovell Williams , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
IPC分类号： H01L29/92
CPC分类号： H01L28/91
摘要： In a disclosed embodiment, a stacked capacitor (100) has bottom, middle and top metal electrode layers (141A, 141B, 141C) interleaved with dielectric layers (142A, 142B) conformally disposed within holes (140A, 140B, 140C) in a protective overcoat or backend dielectric layer (110) over a top metal layer (115) of an integrated circuit (105). A top electrode (155) contacts the top metal electrode layer (141C). A bottom electrode (150) electrically couples an isolated part of the top metal electrode layer (141C) through a bottom electrode via (165A) to a first contact node (135A) in the top metal layer (115) which is in contact with the bottom metal electrode layer (141A). A middle electrode (160) electrically couples a part of the middle metal electrode layer (141B) not covered by the top metal layer (115) through a middle electrode via (165B) to a second contact node (135B) in the top metal electrode layer (115). The sidewalls of the top and middle electrode vias (165A, 165B) are lined with insulating material to electrically isolate the metal electrode layer ends.
摘要翻译：在公开的实施例中，叠层电容器（100）具有与保护性地设置在保护孔（140A，140B，140C）内的电介质层（142A，142B）交错的底部，中间和顶部金属电极层（141A，141B，141C）外部涂层或后端电介质层（110）覆盖在集成电路（105）的顶部金属层（115）上。顶部电极（155）接触顶部金属电极层（141C）。底部电极（150）通过（165A）将顶部金属电极层（141C）的隔离部分电耦合到顶部金属层（115）中与第一接触节点（135A）接触的第一接触节点（135A）底部金属电极层（141A）。中间电极（160）将未被顶部金属层（115）覆盖的中间金属电极层（141B）的一部分通过中间电极（165B）电耦合到顶部金属电极中的第二接触节点（135B）层（115）。顶部和中间电极通孔（165A，165B）的侧壁衬有绝缘材料以电绝缘金属电极层端部。

37. 发明申请

US20090200637A1 METHODS AND DEVICES FOR A HIGH-K STACKED CAPACITOR 有权
标题翻译：用于高K堆叠电容器的方法和装置
公开(公告)号：US20090200637A1
公开(公告)日：2009-08-13
申请号：US12029798
申请日：2008-02-12
申请人： Byron Lovell Williams , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
发明人： Byron Lovell Williams , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/91
摘要： An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.
摘要翻译：实施例通常涉及形成电容器的方法。该方法包括在集成电路的保护外涂层或后端电介质层内形成多个孔，并沉积多层金属，每层金属电连接到相关电极。该方法还包括交替地在多层金属之间沉积多层电介质，并将多层金属的底层耦合到集成电路的顶层金属层中的接触节点。

38. 发明申请

US20080293206A1 UNIQUE LDMOS PROCESS INTEGRATION 有权
标题翻译：独特的LDMOS过程集成
公开(公告)号：US20080293206A1
公开(公告)日：2008-11-27
申请号：US11753789
申请日：2007-05-25
申请人： Binghua Hu , Sameer P. Pendharkar , Bill A. Wofford , Qingfeng Wang
发明人： Binghua Hu , Sameer P. Pendharkar , Bill A. Wofford , Qingfeng Wang
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/0653 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 90 or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.
摘要翻译：示例性实施例提供了用于在半导体中形成掺杂区域的制造方法。具体地，可以通过使用图案化光致抗蚀剂（PR）层作为掩模的多个离子注入工艺来形成掺杂区域。可以通过去除硬烘烤步骤以改善图案化PR层的轮廓，使用硬烘焙光刻工艺来形成图案化的PR层。多个离子注入工艺可以以下列顺序执行：使用高能量注入第一掺杂物种; 使用减少的能量和增加的植入角度（例如，约90或更高）注入第一掺杂物种类; 以及使用减少的能量注入第二掺杂剂物质。在各种实施例中，掺杂区域可以用作LDMOS晶体管的双扩散区域。

39. 发明申请

US20080248062A1 Papillomavirus vaccine compositions 有权
标题翻译：乳头瘤病毒疫苗组合物
公开(公告)号：US20080248062A1
公开(公告)日：2008-10-09
申请号：US12074783
申请日：2008-03-06
申请人： Janine T. Bryan , Michelle K. Brownlow , Li Shi , Danilo Casimiro , William L. McClements , Brian K. Meyer , Binghua Hu
发明人： Janine T. Bryan , Michelle K. Brownlow , Li Shi , Danilo Casimiro , William L. McClements , Brian K. Meyer , Binghua Hu
IPC分类号： A61K39/12 , A61P31/12
CPC分类号： A61K39/12 , A61K2039/5258 , A61K2039/55505 , A61K2039/55577 , A61K2039/70 , C12N7/00 , C12N2710/20023 , C12N2710/20034
摘要： The present invention relates to pharmaceutical compositions comprising virus-like particles (VLPs) of HPV, said VLPs adsorbed to an aluminum adjuvant, and an ISCOM-type adjuvant comprising a saponin, cholesterol, and a phospholipid. In preferred embodiments, the aluminum adjuvant comprises amorphous aluminum hydroxyphosphate sulfate. Another aspect of the invention provides multi-dose HPV vaccine formulations comprising HPV VLPs and an antimicrobial preservative selected from the group consisting of: m-cresol, phenol and benzyl alcohol. Also provided are methods of using the disclosed pharmaceutical compositions and formulations to induce an immune response against HPV in a human patient and to prevent HPV infection.
摘要翻译：本发明涉及包含HPV病毒样颗粒（VLP），所述VLP吸附于铝佐剂的ISMA型佐剂和包含皂角苷，胆固醇和磷脂的ISCOM型佐剂的药物组合物。在优选的实施方案中，铝佐剂包括无定形的羟基磷酸氢铝硫酸盐。本发明的另一方面提供了包含HPV VLP和选自间甲酚，苯酚和苄醇的抗微生物防腐剂的多剂量HPV疫苗制剂。还提供了使用所公开的药物组合物和制剂在人类患者中诱导针对HPV的免疫应答并防止HPV感染的方法。

40. 发明授权

US07141455B2 Method to manufacture LDMOS transistors with improved threshold voltage control 有权
标题翻译：用改进的阈值电压控制制造LDMOS晶体管的方法
公开(公告)号：US07141455B2
公开(公告)日：2006-11-28
申请号：US10712455
申请日：2003-11-12
申请人： Binghua Hu , Howard S. Lee , Henry L. Edwards , John Lin , Vladimir N. Bolkhovsky
发明人： Binghua Hu , Howard S. Lee , Henry L. Edwards , John Lin , Vladimir N. Bolkhovsky
IPC分类号： H01L21/332
CPC分类号： H01L21/266 , H01L21/2652 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).
摘要翻译：在外延层（20）中形成双扩散区域（65），（75），（85）。通过在硬烘烤过程之前首先将诸如硼的光注入物质在光致抗蚀剂层中的开口注入，形成双扩散区域。在硬烘烤过程之后，可以将诸如砷的重植入物种植入外延层中。在后续处理（如LOCOS形成）中形成双扩散区。在外延层（20）上形成介电层（120），并且在电介质层（120）之上形成栅极结构（130），（135）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式