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1. 发明申请

US20080293206A1 UNIQUE LDMOS PROCESS INTEGRATION 有权
标题翻译：独特的LDMOS过程集成
公开(公告)号：US20080293206A1
公开(公告)日：2008-11-27
申请号：US11753789
申请日：2007-05-25
申请人： Binghua Hu , Sameer P. Pendharkar , Bill A. Wofford , Qingfeng Wang
发明人： Binghua Hu , Sameer P. Pendharkar , Bill A. Wofford , Qingfeng Wang
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/0653 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 90 or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.
摘要翻译：示例性实施例提供了用于在半导体中形成掺杂区域的制造方法。具体地，可以通过使用图案化光致抗蚀剂（PR）层作为掩模的多个离子注入工艺来形成掺杂区域。可以通过去除硬烘烤步骤以改善图案化PR层的轮廓，使用硬烘焙光刻工艺来形成图案化的PR层。多个离子注入工艺可以以下列顺序执行：使用高能量注入第一掺杂物种; 使用减少的能量和增加的植入角度（例如，约90或更高）注入第一掺杂物种类; 以及使用减少的能量注入第二掺杂剂物质。在各种实施例中，掺杂区域可以用作LDMOS晶体管的双扩散区域。

2. 发明授权

US07713825B2 LDMOS transistor double diffused region formation process 有权
标题翻译： LDMOS晶体管双扩散区形成过程
公开(公告)号：US07713825B2
公开(公告)日：2010-05-11
申请号：US11753789
申请日：2007-05-25
申请人： Binghua Hu , Sameer P. Pendharkar , Bill A. Wofford , Qingfeng Wang
发明人： Binghua Hu , Sameer P. Pendharkar , Bill A. Wofford , Qingfeng Wang
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/0653 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 9° or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.
摘要翻译：示例性实施例提供了用于在半导体中形成掺杂区域的制造方法。具体地，可以通过使用图案化光致抗蚀剂（PR）层作为掩模的多个离子注入工艺来形成掺杂区域。可以通过去除硬烘烤步骤以改善图案化PR层的轮廓，使用硬烘焙光刻工艺来形成图案化的PR层。多个离子注入工艺可以以下列顺序执行：使用高能量注入第一掺杂物种; 使用减少的能量和增加的植入角度（例如，约9°或更高）注入第一掺杂物种类; 以及使用减少的能量注入第二掺杂剂物质。在各种实施例中，掺杂区域可以用作LDMOS晶体管的双扩散区域。

3. 发明授权

US07435659B2 Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process 有权
标题翻译：用于制造具有使用N型掺杂剂形成的取向特征和湿式氧化处理的半导体器件的方法
公开(公告)号：US07435659B2
公开(公告)日：2008-10-14
申请号：US11068117
申请日：2005-02-28
申请人： Binghua Hu , Sameer P. Pendharkar , Bill A. Wofford , Joseph M. Ramirez
发明人： Binghua Hu , Sameer P. Pendharkar , Bill A. Wofford , Joseph M. Ramirez
IPC分类号： H01L21/76
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/2652 , H01L21/823493 , H01L21/8249 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further include oxidizing the substrate using a wet oxidation process, the wet oxidation process and n-type dopant causing a ratio of oxidation of the implanted region to the unimplanted region to be 2:1 or greater, and then removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region.
摘要翻译：本发明提供一种具有对准特征的半导体器件的制造方法。除了其他步骤之外，制造半导体器件的方法可以包括将n型掺杂剂注入衬底中，从而在衬底中形成注入区域和未被注入的区域。该方法可以进一步包括使用湿式氧化法，湿法氧化法和n型掺杂剂使得注入区域与未被注入的区域的氧化比例为2:1或更大，然后除去氧化部分从而在植入区域附近留下对准特征。

4. 发明申请

US20080085569A1 METHOD OF USING ELECTRICAL TEST STRUCTURE FOR SEMICONDUCTOR TRENCH DEPTH MONITOR 有权
标题翻译：使用电子测试结构的半导体TRENCH深度监测器的方法
公开(公告)号：US20080085569A1
公开(公告)日：2008-04-10
申请号：US11531103
申请日：2006-09-12
申请人： Qingfeng Wang , Sameer P. Pendharkar , Binghua Hu
发明人： Qingfeng Wang , Sameer P. Pendharkar , Binghua Hu
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L29/0649 , H01L29/8605
摘要： Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.
摘要翻译：实施例提供了用于电监测半导体器件中的沟槽深度的方法和装置。为了电测量沟槽深度，可以在半导体衬底上的深阱区域中形成夹持电阻器。然后可以在夹持电阻器中形成沟槽。沟槽深度可以通过夹持电阻器的电气测试来确定。所公开的方法和装置可以跨晶片提供统计数据分析，并且可以在作为过程监视器的生产划线中实施。所公开的方法也可用于确定LDMOS晶体管的器件性能。 LDMOS晶体管的导通电阻（Rdson）可以与沟槽深度的电测量相关。

5. 发明授权

US07989232B2 Method of using electrical test structure for semiconductor trench depth monitor 有权
标题翻译：半导体沟槽深度监测仪使用电气测试结构的方法
公开(公告)号：US07989232B2
公开(公告)日：2011-08-02
申请号：US11531103
申请日：2006-09-12
申请人： Qingfeng Wang , Sameer P. Pendharkar , Binghua Hu
发明人： Qingfeng Wang , Sameer P. Pendharkar , Binghua Hu
IPC分类号： H01L21/66 , H01L27/07
CPC分类号： H01L22/12 , H01L29/0649 , H01L29/8605
摘要： Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.
摘要翻译：实施例提供了用于电监测半导体器件中的沟槽深度的方法和装置。为了电测量沟槽深度，可以在半导体衬底上的深阱区域中形成夹持电阻器。然后可以在夹持电阻器中形成沟槽。沟槽深度可以通过夹持电阻器的电气测试来确定。所公开的方法和装置可以跨晶片提供统计数据分析，并且可以在作为过程监视器的生产划线中实现。所公开的方法也可用于确定LDMOS晶体管的器件性能。 LDMOS晶体管的导通电阻（Rdson）可以与沟槽深度的电测量相关。

6. 发明授权

US08264038B2 Buried floating layer structure for improved breakdown 有权
标题翻译：埋地浮层结构，可改善故障
公开(公告)号：US08264038B2
公开(公告)日：2012-09-11
申请号：US12537326
申请日：2009-08-07
申请人： Sameer P. Pendharkar , Binghua Hu , Xinfen Chen
发明人： Sameer P. Pendharkar , Binghua Hu , Xinfen Chen
IPC分类号： H01L29/06 , H01L29/78 , H01L29/73 , H01L27/092 , H01L21/761
CPC分类号： H01L21/761 , H01L21/823892 , H01L29/0623 , H01L29/0653 , H01L29/086 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/7322 , H01L29/7816 , H01L29/7833
摘要： A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.
摘要翻译：公开了一种掩埋层结构，其包括与连接到IC中的组件的相同导电类型的深阱连接的高电压埋层相邻的浮置掩埋层结构。浮置掩埋层结构围绕高压掩埋层并且延伸埋层的耗尽区以减小掩埋层的侧边缘处的峰值电场。当浮动掩埋层结构的尺寸和间距被优化时，连接到掩埋层的阱可被偏压到100伏而不会破坏。添加围绕第一浮动掩埋层结构的第二浮动掩埋层结构允许埋入层的操作高达140伏。具有浮动掩埋层结构的掩埋层结构可以并入DEPMOS晶体管，LDMOS晶体管，埋地集电极npn双极晶体管和隔离CMOS电路中。

7. 发明授权

US08154101B2 High voltage diode with reduced substrate injection 有权
公开(公告)号：US08154101B2
公开(公告)日：2012-04-10
申请号：US12537318
申请日：2009-08-07
申请人： Sameer P. Pendharkar , Binghua Hu
发明人： Sameer P. Pendharkar , Binghua Hu
IPC分类号： H01L29/861
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L27/0629 , H01L29/417 , H01L29/66136
摘要： A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

8. 发明授权

US08309423B2 High voltage diode with reduced substrate injection 有权
标题翻译：具有降低衬底注入的高压二极管
公开(公告)号：US08309423B2
公开(公告)日：2012-11-13
申请号：US13409689
申请日：2012-03-01
申请人： Sameer P. Pendharkar , Binghua Hu
发明人： Sameer P. Pendharkar , Binghua Hu
IPC分类号： H01L29/861
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L27/0629 , H01L29/417 , H01L29/66136
摘要： A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.
摘要翻译：公开了一种高压二极管，其中n型阴极由未接触的重掺杂n型环包围以将注入的孔反射回阴极区域进行复合或收集。重掺杂n型环中的掺杂剂密度优选为阴极中掺杂剂密度的100至10,000倍。重掺杂的n型区通常连接到阴极下方的n型掩埋层。重掺杂的n型环优选地从阴极触点定位至少一个孔扩散长度。所公开的高电压二极管可以集成到集成电路中，而不需要添加工艺步骤。

9. 发明申请

US20090325352A1 METHODS OF FORMING DRAIN EXTENDED TRANSISTORS 有权
标题翻译：排水延伸晶体管的形成方法
公开(公告)号：US20090325352A1
公开(公告)日：2009-12-31
申请号：US12552471
申请日：2009-09-02
申请人： Sameer P. Pendharkar
发明人： Sameer P. Pendharkar
IPC分类号： H01L29/78 , H01L29/36
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/1087 , H01L29/41 , H01L29/41725 , H01L29/42368 , H01L29/66659 , H03K19/00384
摘要： A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.
摘要翻译：晶体管包括第一导电类型的源极区域并与第一半导体区域电连通。晶体管还包括第一导电类型的漏极区域，并且与第一半导体区域不同的第二半导体区域电连通。在第一半导体区域和第二半导体区域之间存在界面。晶体管还包括电压抽头区域，该电压抽头区域至少包括位于比漏极区域更接近界面的位置的部分。还描述了一种混合技术电路。

10. 发明授权

US07414287B2 System and method for making a LDMOS device with electrostatic discharge protection 有权
标题翻译：制造具有静电放电保护功能的LDMOS器件的系统和方法
公开(公告)号：US07414287B2
公开(公告)日：2008-08-19
申请号：US11063312
申请日：2005-02-21
申请人： Sameer P. Pendharkar , Jonathan S. Brodsky
发明人： Sameer P. Pendharkar , Jonathan S. Brodsky
IPC分类号： H01L29/94
CPC分类号： H01L29/66681 , H01L27/088 , H01L29/086 , H01L29/42368 , H01L29/7436 , H01L29/749 , H01L29/7816
摘要： A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.
摘要翻译：半导体器件包括一个或多个LDMOS晶体管和一个更多的SCR-LDMOS晶体管。每个LDMOS晶体管包括第一导电类型的LDMOS阱，在LDMOS阱中形成的第二导电类型的LDMOS源极区，以及由LDMOS阱的LDMOS漂移区分离的第二导电类型的LDMOS漏极区，第二导电类型。每个SCR-LDMOS晶体管包括第一导电类型的SCR-LDMOS阱，形成在SCR-LDMOS阱中的第二导电类型的SCR-LDMOS源区，第二导电类型的SCR-LDMOS漏极区和 SCR-LDMOS漏区和SCR-LDMOS漂移区之间的第一导电类型的阳极区。阳极区域通过第二导电类型的SCR-LDMOS漂移区与SCR-LDMOS阱分离。

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