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31. 发明授权

US07894255B1 Thyristor based memory cell 失效
标题翻译：基于晶闸管的存储单元
公开(公告)号：US07894255B1
公开(公告)日：2011-02-22
申请号：US11881049
申请日：2007-07-25
申请人： Farid Nemati , Scott Robins , Kevin J. Yang
发明人： Farid Nemati , Scott Robins , Kevin J. Yang
IPC分类号： G11C11/34
CPC分类号： G11C11/39 , H01L27/1027 , H01L29/66393 , H01L29/7436
摘要： A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. Each memory cell is separated from other memory cells by shallow trench isolation regions. The memory cell comprises a thyristor body and a gate. The thyristor body has two end region and two base regions. The gate is positioned over and insulated from at least a portion of one base region and offset from another base region. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.
摘要翻译：新的存储单元仅包含一个晶闸管，而不需要包括一个存取晶体管。可以在体硅晶片上制造包含这些存储单元的存储器阵列。每个存储单元通过浅沟槽隔离区与其它存储单元分离。存储单元包括可控硅体和栅极。晶闸管体具有两个端部区域和两个基极区域。栅极定位在一个基极区域的至少一部分上并与另一个基极区域偏移绝缘。第一端区连接到字线，位线和第三线之一。第二端区连接到字线，位线和第三线中的另一端。门连接到字线，位线和第三行的剩余部分。

32. 发明申请

US20090162979A1 THYRISTOR DEVICE WITH CARBON LIFETIME ADJUSTMENT IMPLANT AND ITS METHOD OF FABRICATION 失效
标题翻译：具有碳生物调节植入物的制造装置及其制造方法
公开(公告)号：US20090162979A1
公开(公告)日：2009-06-25
申请号：US12367891
申请日：2009-02-09
申请人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
发明人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
IPC分类号： H01L21/266
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
摘要翻译：在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

33. 发明授权

US07037763B1 Gated-thyristor approach having angle-implanted base region 失效
标题翻译：具有角度注入基极区域的门控晶闸管方法
公开(公告)号：US07037763B1
公开(公告)日：2006-05-02
申请号：US10739859
申请日：2003-12-18
申请人： Farid Nemati , Scott Robins , Andrew E. Horch
发明人： Farid Nemati , Scott Robins , Andrew E. Horch
IPC分类号： H01L21/332
CPC分类号： H01L27/0817 , H01L29/742 , H01L29/7436
摘要： In an example gated-thyristor circuit, formation of thyristor body regions involves an angled implant of a thyristor body region, such as a base region, to mitigate capacitive coupling of a gated voltage pulse from the thyristor gate to a body region that is not underlying the thyristor gate. According to a more particular example embodiment, such a thyristor switches between a current-passing mode and a current blocking mode in response to at least one voltage pulse coupling to an underlying thyristor base region. Using a first ion type to provide one polarity, an immediately-adjacent thyristor base region is angle implanted through an emitter body region that is located to other side of the adjacent thyristor base region. The emitter body region is then implanted using ions of another ion type to provide the opposite polarity. This angle implantation permits definition of the adjacent thyristor base region sufficiently distant from (e.g., underlapping) the gate to mitigate gate-induced leakage to the second body region and the associated junction leakage between thyristor base regions. Applications include a variety of circuits benefiting from fast-switching and/or small-architecture features; example applications include thyristor-based latches and memory cells and power thyristor circuits.
摘要翻译：在示例性的门控晶闸管电路中，晶闸管体区域的形成涉及晶闸管本体区域（例如基极区域）的成角度注入，以缓解门控电压脉冲从晶闸管门极到不是底层的体区域的电容耦合晶闸管门。根据更具体的示例性实施例，这种晶闸管响应于至少一个连接到下游晶闸管基极区域的电压脉冲而在电流通过模式和电流阻塞模式之间切换。使用第一离子型来提供一个极性，通过位于相邻晶闸管基极区域的另一侧的发射体体区域，直接注入相邻的晶闸管基极区域。然后使用另一离子型离子注入发射体体区域以提供相反的极性。该角度注入允许定义足够远离（例如，重叠）栅极的相邻晶闸管基极区域，以减轻栅极引起的泄漏到第二体区域以及晶闸管基极区域之间的相关连结泄漏。应用包括受益于快速切换和/或小型架构特性的各种电路; 示例应用包括基于晶闸管的锁存器和存储器单元和功率晶闸管电路。

34. 发明授权

US06653175B1 Stability in thyristor-based memory device 失效
标题翻译：基于晶闸管的存储器件的稳定性
公开(公告)号：US06653175B1
公开(公告)日：2003-11-25
申请号：US10231805
申请日：2002-08-28
申请人： Farid Nemati , Hyun-Jin Cho , Scott Robins
发明人： Farid Nemati , Hyun-Jin Cho , Scott Robins
IPC分类号： H01L21332
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： A semiconductor device having a thyristor-based memory device exhibits improved stability under adverse operating conditions related to temperature, noise, electrical disturbances and light. In one particular example embodiment of the present invention, a semiconductor device includes a thyristor-based memory device that uses a shunt that effects a leakage current in the thyristor. The thyristor includes a capacitively-coupled control port and anode and cathode end portions. Each of the end portions has an emitter region and an adjacent base region. In one implementation, the current shunt is located between the emitter and base region of one of the end portions of the thyristor and is configured and arranged to shunt low-level current therebetween. In connection with an example embodiment, it has been discovered that shunting current in this manner improves the ability of the device to operate under adverse conditions that would, absent the shunt, result in inadvertent turn on, while keeping the standby current of the memory device to an acceptably low level.
摘要翻译：具有基于晶闸管的存储器件的半导体器件在与温度，噪声，电扰动和光线相关的不利操作条件下表现出改进的稳定性。在本发明的一个具体示例实施例中，半导体器件包括基于晶闸管的存储器件，其使用在晶闸管中产生漏电流的分流器。晶闸管包括电容耦合控制端口和阳极和阴极端部分。每个端部具有发射极区域和相邻的基极区域。在一个实施方案中，电流分流器位于晶闸管的一个端部的发射极和基极区域之间，并且被配置和布置成在它们之间分流低电平电流。结合示例性实施例，已经发现，以这种方式分流电流提高了器件在不利条件下操作的能力，这种不利条件将在不存在分流的情况下导致无意中导通，同时保持存储器件的待机电流达到可接受的低水平。

35. 发明申请

US20090140288A1 HIGH ION/IOFF SOI MOSFET USING BODY VOLTAGE CONTROL 失效
标题翻译：使用体电压控制的高ION / IOFF SOI MOSFET
公开(公告)号：US20090140288A1
公开(公告)日：2009-06-04
申请号：US12368171
申请日：2009-02-09
申请人： Zachary K. Lee , Farid Nemati , Scott Robins
发明人： Zachary K. Lee , Farid Nemati , Scott Robins
IPC分类号： H01L27/102 , H01L29/10
CPC分类号： H01L27/1203 , H01L29/7841
摘要： A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.
摘要翻译：半导体器件可以包括部分耗尽的SOI MOSFET，其具有设置在源极和漏极之间的浮体区域。可以驱动浮体区域以接收注入的载流子，以在MOSFET的操作期间调整其电位。在特定的情况下，MOSFET可以包括与MOSFET的漏极/源极区域和与体区域相对的一侧连续关系的半导体材料的另一区域。该附加区域可以形成为具有与漏极/源极相反的类型的导电性，并且可以建立每个主体，漏极/源极和附加区域的有效双极器件。其几何形状和掺杂可被设计成建立足以帮助载流子注入浮体区域的传输增益，但足够小以防止与MOSFET的互锁。

36. 发明授权

US07075122B1 Thyristor device with carbon lifetime adjustment implant and its method of fabrication 失效
公开(公告)号：US07075122B1
公开(公告)日：2006-07-11
申请号：US10670881
申请日：2003-09-25
申请人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
发明人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
IPC分类号： H01L29/72
CPC分类号： H01L27/0817 , H01L29/7436 , H01L29/7455
摘要： In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

37. 发明授权

US08576649B1 Sense amplifiers and operations thereof 失效
标题翻译：感应放大器及其操作
公开(公告)号：US08576649B1
公开(公告)日：2013-11-05
申请号：US13172017
申请日：2011-06-29
申请人： Farid Nemati
发明人： Farid Nemati
IPC分类号： G11C7/00
CPC分类号： G11C11/39 , G11C7/065 , G11C11/406
摘要： Sense amplifiers and operations thereof are described. More particularly, embodiments of integrated circuit having a sense amplifier coupled to a first bitline and a second bitline of a memory array are described. The sense amplifier generally includes: a latch circuit and a group select input/output circuit, as well as read, reference voltage, and precharge circuitry. Further described is an embodiment of a method for a refresh operation. First data states of a group of memory cells of an array are read and written back as second data states without changing voltages at sense nodes of the latch circuits from the reading, where the second data states are an inverse of the first data states.
摘要翻译：描述了检测放大器及其操作。更具体地，描述了具有耦合到存储器阵列的第一位线和第二位线的读出放大器的集成电路的实施例。读出放大器通常包括：锁存电路和组选择输入/输出电路，以及读取，参考电压和预充电电路。进一步描述了刷新操作的方法的实施例。作为第二数据状态读取并写入阵列的一组存储器单元的第一数据状态，而不改变锁存电路的读出节点处的读取电压，其中第二数据状态是第一数据状态的倒数。

38. 发明申请

US20130182486A1 MEMORY CELLS HAVING A COMMON GATE TERMINAL 有权
公开(公告)号：US20130182486A1
公开(公告)日：2013-07-18
申请号：US13350061
申请日：2012-01-13
申请人： Rajesh N. Gupta , Farid Nemati
发明人： Rajesh N. Gupta , Farid Nemati
IPC分类号： G11C11/21 , H01L21/8239
CPC分类号： H01L27/2454 , G11C11/161 , G11C11/1659 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1608
摘要： Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.

39. 发明授权

US06967358B2 Thyristor-type memory device 失效
标题翻译：晶闸管型存储器件
公开(公告)号：US06967358B2
公开(公告)日：2005-11-22
申请号：US10777453
申请日：2004-02-12
申请人： Farid Nemati , James D. Plummer
发明人： Farid Nemati , James D. Plummer
IPC分类号： G11C11/41 , G11C11/39 , H01L21/8244 , H01L27/06 , H01L27/11 , H01L29/417 , H01L29/423 , H01L29/74 , H01L29/87
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.
摘要翻译：晶闸管器件可用于实现包括高密度存储单元阵列和单个单元电路的各种半导体存储器电路。在一个示例性实施例中，晶闸管器件包括具有相反极性的掺杂区域，以及用于向存储器单元提供读取和写入访问的第一字线。第二字线例如通过增强晶闸管器件从高电导状态到高电导状态的切换而位于与用于写入操作的晶闸管器件的掺杂区域中的一个的绝缘材料相邻并由绝缘材料隔开的位置低电导状态和/或从低电导状态到高电导状态。可以实现这种类型的存储器电路，以显着降低待机功耗和访问时间。

40. 发明授权

US06885581B2 Dynamic data restore in thyristor-based memory device 失效
标题翻译：基于晶闸管的存储器件中的动态数据恢复
公开(公告)号：US06885581B2
公开(公告)日：2005-04-26
申请号：US10472737
申请日：2002-04-05
申请人： Farid Nemati , Hyun-Jin Cho , Robert Homan Igehy
发明人： Farid Nemati , Hyun-Jin Cho , Robert Homan Igehy
IPC分类号： G11C7/00 , G11C11/00 , G11C11/39 , H01L29/866
CPC分类号： G11C11/39
摘要： A dynamically-operating restoration circuit (106) is used to apply a voltage or current restore pulse signal to thyristor-based memory cells (108) and therein restore data in the cell using the internal positive feedback loop of the thyristor (110). In one example implementation, the internal positive feedback loop in the thyristor (110) is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.
摘要翻译：使用动态操作的恢复电路（106）将电压或电流恢复脉冲信号施加到基于晶闸管的存储器单元（108），并且其中使用晶闸管（110）的内部正反馈环路在单元中恢复数据。在一个示例实现中，晶闸管（110）中的内部正反馈环路用于在晶闸管电流下降到保持电流之前恢复器件的导通状态。定义并施加脉冲和/或周期波形以确保晶闸管不从其导通状态释放。晶闸管周期性恢复电流的时间平均值可能低于保持电流阈值。虽然不一定限于基于晶闸管的存储器单元，但是已经发现本发明的各种实施例对于其中使用薄电容耦合晶闸管来提供双向的高速，低功率存储器单元特别有用稳定存储元件

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