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31. 发明授权

US06174814B1 Method for producing a crack stop for interlevel dielectric layers 失效
标题翻译：制备层间电介质层裂缝的方法
公开(公告)号：US06174814B1
公开(公告)日：2001-01-16
申请号：US09557537
申请日：2000-04-25
申请人： Robert F. Cook , Eduardo Garcia , Nancy A. Greco , Stephen E. Greco , Ernest N. Levine
发明人： Robert F. Cook , Eduardo Garcia , Nancy A. Greco , Stephen E. Greco , Ernest N. Levine
IPC分类号： H01L2100
CPC分类号： H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The propagation of a crack from the surface of the dielectric layer of an integrated circuit, through to the underlying circuit elements, is prevented by controlling the interface between the outermost, dielectric layer or layers and the inner layer or layers of the integrated circuit construction. The interface is weakened so that a crack that encounters the interface is caused to propagate in a horizontal manner, along the interface, preventing propagation of the crack in a direction that would be harmful to the manufactured article. This is preferably accomplished with multiple layers of material, each of which is made capable of redirecting (deflecting) the crack. Deflection of the crack, and arrest of the deflected crack along the interface, is made possible by controlling the fracture resistance of the interface.
摘要翻译：通过控制最外层，电介质层或集成电路结构的内层或多层之间的界面，可以防止裂纹从集成电路介质层的表面传播到下面的电路元件。界面被削弱，使得遇到界面的裂缝沿着界面以水平的方式传播，从而防止裂纹沿着对制成品有害的方向的传播。这优选地通过多层材料实现，每层材料能够使裂缝重定向（偏转）。通过控制界面的抗断裂性，使得裂纹的偏转和沿着界面的偏转裂纹的阻滞成为可能。

32. 发明授权

US4997746A Method of forming conductive lines and studs 失效
标题翻译：形成导线和螺柱的方法
公开(公告)号：US4997746A
公开(公告)日：1991-03-05
申请号：US274895
申请日：1988-11-22
申请人： Nancy A. Greco , Stephen E. Greco
发明人： Nancy A. Greco , Stephen E. Greco
IPC分类号： H01L21/3213 , H01L21/3205 , H01L21/768 , H05K3/46
CPC分类号： H01L21/76885 , H05K3/4647 , Y10S438/948
摘要： A method is provided for forming a conductive stud and line over a surface, comprising the steps of: forming at least a first layer of material over the region on the surface whereat the conductive stud and line are to be formed; forming a layer of dual image photoresist over the material; exposing the dual image potoresist to radiation so as to form at least first and second regions exhibiting different development characteristics; developing the first region so as to expose a portion of the material; removing the exposed portion of the material so as to define the position of one of the conductive line or stud; developing the second region to expose more of the material; and removing the newly exposed portion of material so as to define the position of the other of the conductive line or stud.
摘要翻译：提供一种用于在表面上形成导电柱和线的方法，包括以下步骤：在要形成导电柱和线的表面上的区域上形成至少第一层材料; 在材料上形成双重图像光致抗蚀剂层; 将双重图像暴露于辐射，以形成具有不同显影特性的至少第一和第二区域; 显影第一区域以暴露部分材料; 去除所述材料的暴露部分以便限定所述导电线或螺柱之一的位置; 开发第二个区域以暴露更多的材料; 以及去除新露出的材料部分，以限定另一导电线或螺柱的位置。

33. 发明授权

US08053862B2 Integrated circuit fuse 有权
标题翻译：集成电路保险丝
公开(公告)号：US08053862B2
公开(公告)日：2011-11-08
申请号：US12054876
申请日：2008-03-25
申请人： Stephen E. Greco
发明人： Stephen E. Greco
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L21/7682 , H01L21/76892 , H01L2924/0002 , Y10S430/146 , H01L2924/00
摘要： An integrated circuit and a fuse therefore are disclosed. The integrated circuit fuses includes a plurality of terminals coupled by a fuse element, wherein the fuse element is located in a non-last metal layer and/or wherein each terminal is fully-landed on an upper surface of a wire of the fuse element. As a result, there is no explosion that causes damage to surrounding material. In addition, use of the wet etchant allows positioning of a fuse in any metal layer including any non-last metal layer, thus increasing design possibilities.
摘要翻译：因此，公开了集成电路和保险丝。集成电路保险丝包括多个通过熔丝元件连接的端子，其中熔丝元件位于非最后金属层和/或其中每个端子完全降落在熔丝元件的导线的上表面上。因此，没有爆炸造成周围材料的损坏。此外，使用湿蚀刻剂允许在包括任何非最后金属层的任何金属层中定位熔丝，从而增加设计可能性。

34. 发明申请

US20110184715A1 SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN 有权
标题翻译：用于电路设计中的图形的预测问题的系统和方法
公开(公告)号：US20110184715A1
公开(公告)日：2011-07-28
申请号：US13080148
申请日：2011-04-05
申请人： Timothy A. BRUNNER , Stephen E. Greco , Bernard R. Liegl , Hua Xiang
发明人： Timothy A. BRUNNER , Stephen E. Greco , Bernard R. Liegl , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G03F1/144 , G03F1/36 , G03F1/70 , G03F7/705
摘要： A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.
摘要翻译：提供了一种系统和方法，其预测电路设计中的光刻的有问题的区域，更具体地，其使用来自建模工具的建模数据来准确地预测有问题的光刻区域。该方法包括识别模拟晶片的多个瓦片的表面高度，以及数学上模拟光刻工具以确定用于多个瓦片的曝光的最佳焦点平面。

35. 发明授权

US07701035B2 Laser fuse structures for high power applications 失效
标题翻译：用于大功率应用的激光熔丝结构
公开(公告)号：US07701035B2
公开(公告)日：2010-04-20
申请号：US11164640
申请日：2005-11-30
申请人： Stephen E. Greco , Erik L. Hedberg , Dae-Young Jung , Paul S. McLaughlin , Christopher D. Muzzy , Norman J. Rohrer , Jean E. Wynne
发明人： Stephen E. Greco , Erik L. Hedberg , Dae-Young Jung , Paul S. McLaughlin , Christopher D. Muzzy , Norman J. Rohrer , Jean E. Wynne
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (12a, 12b), at least one conductive fusible link (14), first and second connection elements (20a, 20b), and first and second metal lines (22a, 22b). The conductive supporting elements (12a, 12b), the conductive fusible link (14), and the metal lines (22a, 22b) are located at a first metal level (3), while the connect elements (20a, 20b) are located at a second, different metal level (4) and are connected to the conductive supporting elements (12a, 12b) and the metal lines (22a, 22b) by conductive via stacks (18a, 18b, 23a, 23b) that extend between the first and second metal levels (3, 4).
摘要翻译：本发明涉及一种用于大功率应用的激光熔丝结构。具体地，本发明的激光熔丝结构包括第一和第二导电支撑元件（12a，12b），至少一个导电熔丝（14），第一和第二连接元件（20a，20b）以及第一和第二金属线（22a，22b）。导电支撑元件（12a，12b），导电熔丝（14）和金属线（22a，22b）位于第一金属层（3）处，而连接元件（20a，20b）位于第二不同的金属层（4），并且通过在第一和第二金属层之间延伸的导电通孔叠层（18a，18b，23a，23b）连接到导电支撑元件（12a，12b）和金属线（22a，22b）第二金属含量（3,4）。

36. 发明申请

US20100031221A1 VIA DENSITY CHANGE TO IMPROVE WAFER SURFACE PLANARITY 有权
标题翻译：通过密度变化改善水面平面度
公开(公告)号：US20100031221A1
公开(公告)日：2010-02-04
申请号：US12183313
申请日：2008-07-31
申请人： Stephen E. Greco
发明人： Stephen E. Greco
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Changing a via density for viafill vias to improve wafer surface planarity for later photolithography is provided, in one embodiment, by obtaining a circuit design including a plurality of viafill vias having differing via density across the circuit design, each viafill via interconnecting non-functional metal fill shapes in different layers of the circuit design; selecting a region of the circuit design to evaluate using an evaluation window; determining a via density within the evaluation window; and changing a number of viafill vias within the region in the circuit design in response to the via density being different than a threshold via density that is selected such that a coating deposited over the plurality of vias presents a substantially planar surface.
摘要翻译：在一个实施例中，通过获得包括跨越电路设计的具有不同通孔密度的多个通孔填充通孔的电路设计，提供了用于通孔填充孔的通孔密度以改善用于后续光刻的晶片表面平面度，每个通孔互连非功能性金属填充形状在不同层次的电路设计; 选择电路设计的区域以使用评估窗口进行评估; 确定评估窗口内的通路密度; 以及响应于所述通孔密度不同于选定的阈值通孔密度，使得沉积在所述多个通孔上的涂层呈现基本平坦的表面，在所述电路设计中的所述区域内改变多个通孔填充孔。

37. 发明申请

US20090265679A1 SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN 有权
标题翻译：用于电路设计中的图形的预测问题的系统和方法
公开(公告)号：US20090265679A1
公开(公告)日：2009-10-22
申请号：US12104585
申请日：2008-04-17
申请人： Timothy A. Brunner , Stephen E. Greco , Bernhard R. Liegl , Hua Xiang
发明人： Timothy A. Brunner , Stephen E. Greco , Bernhard R. Liegl , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G03F1/144 , G03F1/36 , G03F1/70 , G03F7/705
摘要： A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.
摘要翻译：提供了一种系统和方法，其预测电路设计中的光刻的有问题的区域，更具体地，其使用来自建模工具的建模数据来准确地预测有问题的光刻区域。该方法包括识别模拟晶片的多个瓦片的表面高度，以及数学上模拟光刻工具以确定用于多个瓦片的曝光的最佳焦点平面。

38. 发明授权

US07390615B2 Integrated circuit fuse and method of opening 有权
标题翻译：集成电路保险丝和开路方法
公开(公告)号：US07390615B2
公开(公告)日：2008-06-24
申请号：US10604011
申请日：2003-06-20
申请人： Stephen E. Greco
发明人： Stephen E. Greco
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L23/5256 , H01L21/7682 , H01L21/76892 , H01L2924/0002 , Y10S430/146 , H01L2924/00
摘要： An integrated circuit, a fuse therefor and fuse opening method are disclosed. The method implements fuse opening using a wet etchant. As a result, there is no explosion that causes damage to surrounding material. In addition, use of the wet etchant allows positioning of a fuse in any metal layer including any non-last metal layer, thus increasing design possibilities.
摘要翻译：公开了一种集成电路，其保险丝和保险丝打开方法。该方法使用湿蚀刻剂实现保险丝开口。因此，没有爆炸造成周围材料的损坏。此外，使用湿蚀刻剂允许在包括任何非最后金属层的任何金属层中定位熔丝，从而增加设计可能性。

39. 发明授权

US07135398B2 Reliable low-k interconnect structure with hybrid dielectric 有权
标题翻译：具有混合电介质的可靠的低k互连结构
公开(公告)号：US07135398B2
公开(公告)日：2006-11-14
申请号：US10901868
申请日：2004-07-29
申请人： John A. Fitzsimmons , Stephen E. Greco , Jia Lee , Stephen M. Gates , Terry Spooner , Matthew S. Angyal , Habib Hichri , Theordorus E. Standaert , Glenn A. Biery
发明人： John A. Fitzsimmons , Stephen E. Greco , Jia Lee , Stephen M. Gates , Terry Spooner , Matthew S. Angyal , Habib Hichri , Theordorus E. Standaert , Glenn A. Biery
IPC分类号： H01L21/4763
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.
摘要翻译：公开了一种具有混合电介质的高级后端（BEOL）互连结构。用于通孔电平的层间电介质（ILD）优选地不同于线路电平的ILD。在优选实施例中，通孔级ILD由低k SiCOH材料形成，并且线级ILD由低k聚合物热固性材料形成。

40. 发明授权

US06727589B2 Dual damascene flowable oxide insulation structure and metallic barrier 有权
标题翻译：双镶嵌可流动氧化物绝缘结构和金属屏障
公开(公告)号：US06727589B2
公开(公告)日：2004-04-27
申请号：US09725862
申请日：2000-11-30
申请人： Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
发明人： Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/31116 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/7684
摘要： A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.
摘要翻译：一种通过氧化FOX绝缘体的侧壁来保护半导体中的可流动的氧化物绝缘体的方法和结构，可选地将氧化的FOX侧壁氮化，然后覆盖包括侧壁在内的FOX绝缘体中的槽或多个槽的所有表面，导电二级保护层。在多层镶嵌结构中，FOX绝缘体的表面也被氧化，在其上沉积另外的氧化物层，并且沉积在氧化物层上的氮化物层。然后重复步骤以获得可比较的镶嵌结构。材料可以变化，并且每个镶嵌层可以是单镶嵌层或双镶嵌层。

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