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1. 发明授权

US06339022B1 Method of annealing copper metallurgy 失效
标题翻译：铜冶炼退火方法
公开(公告)号：US06339022B1
公开(公告)日：2002-01-15
申请号：US09475712
申请日：1999-12-30
申请人： Arne W. Ballantine , Edward C. Cooney, III , George A. Dunbar, III , Cheryl G. Faltermeier , Jeffrey D. Gilbert , Ronald D. Goldblatt , Nancy A. Greco , Stephen E. Greco , Frank V. Liucci , Glenn Robert Miller , Bruce A. Root , Andrew H. Simon , Anthony K. Stamper , Ronald A. Warren , David H. Yao
发明人： Arne W. Ballantine , Edward C. Cooney, III , George A. Dunbar, III , Cheryl G. Faltermeier , Jeffrey D. Gilbert , Ronald D. Goldblatt , Nancy A. Greco , Stephen E. Greco , Frank V. Liucci , Glenn Robert Miller , Bruce A. Root , Andrew H. Simon , Anthony K. Stamper , Ronald A. Warren , David H. Yao
IPC分类号： H01L2144
CPC分类号： H01L21/02074 , H01L21/3212 , H01L21/7684
摘要： A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.
摘要翻译：一种通过化学机械平面化方法提高具有铜冶金平面化的半导体器件的生产率的方法，该方法包括含有导体钝化剂（如苯并三唑）的浆料，其中使用非氧化退火来除去可能干扰的任何残余物在进一步的金属化步骤之前，在衬底上的导电焊盘的机械探测。退火可以通过几种技术中的任何一种进行，包括真空室，标准炉或快速热退火。

2. 发明授权

US06091131A Integrated circuit having crack stop for interlevel dielectric layers 失效
标题翻译：集成电路具有层间电介质层的裂纹停止
公开(公告)号：US06091131A
公开(公告)日：2000-07-18
申请号：US67905
申请日：1998-04-28
申请人： Robert F. Cook , Eduardo Garcia , Nancy A. Greco , Stephen E. Greco , Ernest N. Levine
发明人： Robert F. Cook , Eduardo Garcia , Nancy A. Greco , Stephen E. Greco , Ernest N. Levine
IPC分类号： H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , H01L2924/0002
摘要： The propagation of a crack from the surface of the dielectric layer of an integrated circuit, through to the underlying circuit elements, is prevented by controlling the interface between the outermost, dielectric layer or layers and the inner layer or layers of the integrated circuit construction. The interface is weakened so that a crack that encounters the interface is caused to propagate in a horizontal manner, along the interface, preventing propagation of the crack in a direction that would be harmful to the manufactured article. This is preferably accomplished with multiple layers of material, each of which is made capable of redirecting (deflecting) the crack. Deflection of the crack, and arrest of the deflected crack along the interface, is made possible by controlling the fracture resistance of the interface.
摘要翻译：通过控制最外层，电介质层或集成电路结构的内层或多层之间的界面，可以防止裂纹从集成电路介质层的表面传播到下面的电路元件。界面被削弱，使得遇到界面的裂缝沿着界面以水平的方式传播，从而防止裂纹沿着对制成品有害的方向的传播。这优选地通过多层材料实现，每层材料能够使裂缝重定向（偏转）。通过控制界面的抗断裂性，使得裂纹的偏转和沿着界面的偏转裂纹的阻滞成为可能。

3. 发明授权

US06174814B1 Method for producing a crack stop for interlevel dielectric layers 失效
标题翻译：制备层间电介质层裂缝的方法
公开(公告)号：US06174814B1
公开(公告)日：2001-01-16
申请号：US09557537
申请日：2000-04-25
申请人： Robert F. Cook , Eduardo Garcia , Nancy A. Greco , Stephen E. Greco , Ernest N. Levine
发明人： Robert F. Cook , Eduardo Garcia , Nancy A. Greco , Stephen E. Greco , Ernest N. Levine
IPC分类号： H01L2100
CPC分类号： H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The propagation of a crack from the surface of the dielectric layer of an integrated circuit, through to the underlying circuit elements, is prevented by controlling the interface between the outermost, dielectric layer or layers and the inner layer or layers of the integrated circuit construction. The interface is weakened so that a crack that encounters the interface is caused to propagate in a horizontal manner, along the interface, preventing propagation of the crack in a direction that would be harmful to the manufactured article. This is preferably accomplished with multiple layers of material, each of which is made capable of redirecting (deflecting) the crack. Deflection of the crack, and arrest of the deflected crack along the interface, is made possible by controlling the fracture resistance of the interface.
摘要翻译：通过控制最外层，电介质层或集成电路结构的内层或多层之间的界面，可以防止裂纹从集成电路介质层的表面传播到下面的电路元件。界面被削弱，使得遇到界面的裂缝沿着界面以水平的方式传播，从而防止裂纹沿着对制成品有害的方向的传播。这优选地通过多层材料实现，每层材料能够使裂缝重定向（偏转）。通过控制界面的抗断裂性，使得裂纹的偏转和沿着界面的偏转裂纹的阻滞成为可能。

4. 发明授权

US4997746A Method of forming conductive lines and studs 失效
标题翻译：形成导线和螺柱的方法
公开(公告)号：US4997746A
公开(公告)日：1991-03-05
申请号：US274895
申请日：1988-11-22
申请人： Nancy A. Greco , Stephen E. Greco
发明人： Nancy A. Greco , Stephen E. Greco
IPC分类号： H01L21/3213 , H01L21/3205 , H01L21/768 , H05K3/46
CPC分类号： H01L21/76885 , H05K3/4647 , Y10S438/948
摘要： A method is provided for forming a conductive stud and line over a surface, comprising the steps of: forming at least a first layer of material over the region on the surface whereat the conductive stud and line are to be formed; forming a layer of dual image photoresist over the material; exposing the dual image potoresist to radiation so as to form at least first and second regions exhibiting different development characteristics; developing the first region so as to expose a portion of the material; removing the exposed portion of the material so as to define the position of one of the conductive line or stud; developing the second region to expose more of the material; and removing the newly exposed portion of material so as to define the position of the other of the conductive line or stud.
摘要翻译：提供一种用于在表面上形成导电柱和线的方法，包括以下步骤：在要形成导电柱和线的表面上的区域上形成至少第一层材料; 在材料上形成双重图像光致抗蚀剂层; 将双重图像暴露于辐射，以形成具有不同显影特性的至少第一和第二区域; 显影第一区域以暴露部分材料; 去除所述材料的暴露部分以便限定所述导电线或螺柱之一的位置; 开发第二个区域以暴露更多的材料; 以及去除新露出的材料部分，以限定另一导电线或螺柱的位置。

5. 发明授权

US06083823A Metal deposition process for metal lines over topography 失效
公开(公告)号：US06083823A
公开(公告)日：2000-07-04
申请号：US672878
申请日：1996-06-28
申请人： Parth P. Dave , Nancy A. Greco , Ernest N. Levine , Darryl D. Restaino
发明人： Parth P. Dave , Nancy A. Greco , Ernest N. Levine , Darryl D. Restaino
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76877
摘要： A metal layer is formed at high deposition rate over severe topography by a two step process including formation of a seed layer by cold deposition followed by a second portion of the metal layer deposited at a temperature approximating but below a temperature at which metal from a lower metal layer can extrude through vias reaching thereto. The seed layer is preferably limited to a thickness at which the conformality of the cold-deposited metal will not significantly increase severity of surface topography, generally about one-fourth the thickness of the hot-deposited layer. Via connections are formed without voids and a more planar metal layer surface is formed which allows formation of a protective/anti-reflective layer with good integrity while enhancing subsequent lithographic patterning, thereby eliminating alteration of metal surface chemistry by resist developers and resultant residual metal included within the severe topography.

6. 发明授权

US4975141A Laser ablation for plasma etching endpoint detection 失效
标题翻译：激光烧蚀等离子蚀刻终点检测
公开(公告)号：US4975141A
公开(公告)日：1990-12-04
申请号：US501572
申请日：1990-03-30
申请人： Nancy A. Greco , Joseph P. Nogay
发明人： Nancy A. Greco , Joseph P. Nogay
IPC分类号： H01L21/302 , G01B11/06 , H01J37/32 , H01L21/3065
CPC分类号： H01J37/32935 , G01B11/0683 , Y10S438/94
摘要： A method for detecting the endpoint in an etching process including the steps of: providing a structure to be etched including at least a first layer of material overlying a second layer of material; ablating an aperture in the first layer using a beam of coherent electromagnetic radiation so as to expose a portion of the second layer; exposing the structure to an etchant for etching the second layer; and monitoring the second layer using the ablated aperture so as to detect an endpoint for the etching process.

7. 发明授权

US07480990B2 Method of making conductor contacts having enhanced reliability 失效
标题翻译：制造具有增强的可靠性的导体接触的方法
公开(公告)号：US07480990B2
公开(公告)日：2009-01-27
申请号：US11306668
申请日：2006-01-06
申请人： John A. Fitzsimmons , William J. Cote , Nancy A. Greco , Thomas H. Ivers , Steven Moskowitz
发明人： John A. Fitzsimmons , William J. Cote , Nancy A. Greco , Thomas H. Ivers , Steven Moskowitz
IPC分类号： H05K3/02 , H01L21/302
CPC分类号： H01L21/76826 , H01L21/76802 , H01L21/76807 , H01L21/76825 , Y10T29/49117 , Y10T29/49155 , Y10T29/49165
摘要： Methods for forming conductor contacts provide for etching through a capping layer located upon a conductor contact region within a substrate. A first pair of methods provide for etching through at least a lower thickness of the capping layer with other than a reactive ion etch to provide an exposed conductor contact region. A partially overlapping second pair of methods provides for converting at least an upper thickness of the capping layer to a converted material layer that is removed incident to providing an exposed conductor contact region. As adjunct to any of the methods, a liner layer is formed and located upon the exposed conductor contact region in absence of an undesirable reactive environment.
摘要翻译：用于形成导体触点的方法提供了通过位于衬底内的导体接触区域上的覆盖层的蚀刻。第一对方法提供用除了反应离子蚀刻之外的至少较薄厚度的覆盖层的蚀刻以提供暴露的导体接触区域。部分重叠的第二对方法提供了将覆盖层的至少上部厚度转换成被去除的转换材料层，以提供暴露的导体接触区域。作为任何方法的辅助，在没有不期望的反应性环境的情况下，形成衬里层并且位于暴露的导体接触区域上。

8. 发明授权

US07468124B2 Method and apparatus for copper corrosion prevention during wet clean 失效
标题翻译：湿法清洁时铜腐蚀预防的方法和装置
公开(公告)号：US07468124B2
公开(公告)日：2008-12-23
申请号：US11382802
申请日：2006-05-11
申请人： Nancy A. Greco , Kimberly F. Hooper , Kevin S. Petrarca
发明人： Nancy A. Greco , Kimberly F. Hooper , Kevin S. Petrarca
IPC分类号： C23F13/04
CPC分类号： C23F13/04 , H01L21/02063 , H01L21/67057
摘要： A method and apparatus for cleaning a wafer with a metal exposed through an insulator, through the use of a wet cleaning tank in concert with a feedback system on the potential difference between two leads of the wet cleaning tank. The cleaning tank has a bath in which the wafer and the two leads are immersed. The potential difference between the two leads is regulated when the feedback system detects a change in the potential across the two leads.
摘要翻译：一种通过使用湿式清洗槽与反馈系统一起使用通过绝缘子暴露的金属来清洁晶片的方法和装置，该方法和装置关于湿式清洗槽的两根引线之间的电位差。清洗槽具有浸没晶片和两根引线的槽。当反馈系统检测到两个引线上的电位变化时，两个引线之间的电位差被调节。

9. 发明授权

US4816112A Planarization process through silylation 失效
标题翻译：通过甲硅烷基化的平面化过程
公开(公告)号：US4816112A
公开(公告)日：1989-03-28
申请号：US923779
申请日：1986-10-27
申请人： Garth A. Brooks , Nancy A. Greco
发明人： Garth A. Brooks , Nancy A. Greco
IPC分类号： H01L21/302 , G03F7/16 , H01L21/3065 , H01L21/3105 , H01L21/312 , H01L21/3205 , H01L21/768 , B44C1/22 , C03C15/00 , C03C25/06 , B29C37/00
CPC分类号： G03F7/162 , H01L21/31051 , H01L21/3121 , H01L21/76819
摘要： Disclosed is a process for forming a planarized multilevel ship wiring structure. Starting from a substrate having thereon at least a metal stud serving as vertical wiring between two levels of metallization, a quartz layer is deposited, obtaining a non-planar structure. A thick planarizing photoactive photoresist is applied. The photoresist is converted by silylation process into a silicate having substantially the same etch rate as that of quartz. Silylation is accomplished by, for example, subjecting the resist to a bath of hexamethyldisilazane, hexamethylcyclotrisilazene, octamethylcyclotetrasilazane, N,N,dimethylaminotrimethylsilane or N,N,diethylaminotrimethylsilane, for a period of time determined by the thickness of the resist. Unwanted portions of the silylated resist and quartz are etched back at 1:1 etch rate ratio to the level of the stud.
摘要翻译：公开了一种形成平面化多层船舶布线结构的方法。从其上具有至少一个用作两层金属化之间的垂直布线的金属螺柱的基板开始，沉积石英层，获得非平面结构。应用厚平坦化的光致抗蚀剂。光致抗蚀剂通过甲硅烷化方法转化为具有与石英基本相同的蚀刻速率的硅酸盐。通过例如使抗蚀剂经受由抗蚀剂的厚度确定的时间，使抗蚀剂经受六甲基二硅氮烷，六甲基环三硅氮烷，八甲基环四硅氮烷，N，N，二甲基氨基三甲基硅烷或N，N，二乙基氨基三甲基硅烷的浴的洗涤来实现。甲硅烷基化抗蚀剂和石英的不需要的部分以1:1的蚀刻速率比回蚀刻到螺柱的水平。

10. 发明授权

US08839256B2 Utilization of special purpose accelerators using general purpose processors 有权
标题翻译：使用通用处理器的专用加速器
公开(公告)号：US08839256B2
公开(公告)日：2014-09-16
申请号：US12797201
申请日：2010-06-09
申请人： Heather D. Achilles , Giora Biran , Amit Golander , Nancy A. Greco
发明人： Heather D. Achilles , Giora Biran , Amit Golander , Nancy A. Greco
IPC分类号： G06F9/46 , G06F15/00 , G06F15/76 , G06F9/50
CPC分类号： G06F9/505 , Y02D10/22
摘要： A novel and useful system and method of improving the utilization of a special purpose accelerator in a system incorporating a general purpose processor. In some embodiments, the current queue status of the special purpose accelerator is periodically monitored using a background monitoring process/thread and the current queue status is stored in a shared memory. A shim redirection layer added a priori to a library function task determines at runtime and in user space whether to execute the library function task on the special purpose accelerator or the general purpose processor. At runtime, using the shim redirection layer and based on the current queue status, it is determined whether to execute the library function task on the special purpose accelerator or on the general purpose processor.
摘要翻译：一种改进在包含通用处理器的系统中专用加速器的利用的新颖且有用的系统和方法。在一些实施例中，使用后台监视进程/线程周期性地监视专用加速器的当前队列状态，并且将当前队列状态存储在共享存储器中。在库函数任务中先前添加的垫片重定向层在运行时和用户空间中确定是否在专用加速器或通用处理器上执行库函数任务。在运行时，使用垫片重定向层并基于当前队列状态，确定是否在专用加速器或通用处理器上执行库函数任务。

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