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31. 发明申请

US20080035992A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080035992A1
公开(公告)日：2008-02-14
申请号：US11836383
申请日：2007-08-09
申请人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
发明人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/2815 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L29/7828
摘要： This semiconductor device comprises a drift layer of a first conductivity type formed on a drain layer of a first conductivity type, and a drain electrode electrically connected to the drain layer. A semiconductor base layer of a second conductivity type is formed in a surface of the drift layer, and a source region of a first conductivity type is further formed in the semiconductor base layer.A source electrode is electrically connected to the source region and a semiconductor base layer. Plural gate electrodes are formed through a gate insulation film so that a semiconductor base layer may be sandwiched by the gate electrodes. The width of the semiconductor base layer sandwiched by the gate electrodes is 0.3 micrometers or less.
摘要翻译：该半导体器件包括形成在第一导电类型的漏极层上的第一导电类型的漂移层和电连接到漏极层的漏电极。在漂移层的表面上形成第二导电类型的半导体基底层，并且在半导体基底层中进一步形成第一导电类型的源极区。源电极电连接到源区和半导体基层。多个栅电极通过栅极绝缘膜形成，使得半导体基底层可以被栅电极夹持。被栅电极夹持的半导体基底层的宽度为0.3微米以下。

32. 发明申请

US20070194375A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070194375A1
公开(公告)日：2007-08-23
申请号：US11674337
申请日：2007-02-13
申请人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Syotaro Ono , Miwako Akiyama
发明人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Syotaro Ono , Miwako Akiyama
IPC分类号： H01L29/94
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/7813
摘要： This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.
摘要翻译：该半导体器件包括形成在第一半导体层表面上的第一导电类型的第一半导体层，第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。第二导电类型的列层以一定间隔在基底层下的外延层中重复形成。形成沟槽以穿透基底层以到达外延层; 并且栅电极经由栅极绝缘膜形成在沟槽中。在基底层的周边的端部区域，在外延层上形成第二导电类型的端接层。端接层形成为具有大于基底层的结深度的结深度。

33. 发明授权

US07230297B2 Trench-gated MOSFET including schottky diode therein 有权
标题翻译：沟槽栅MOSFET，其中包括肖特基二极管
公开(公告)号：US07230297B2
公开(公告)日：2007-06-12
申请号：US11127224
申请日：2005-05-12
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

34. 发明授权

US07227225B2 Semiconductor device having a vertical MOS trench gate structure 失效
标题翻译：具有垂直MOS沟槽栅极结构的半导体器件
公开(公告)号：US07227225B2
公开(公告)日：2007-06-05
申请号：US10829173
申请日：2004-04-22
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933
摘要： A second semiconductor region is formed on a first semiconductor region. A third semiconductor region is formed on a part of the second semiconductor region. A trench ranges from a surface of the third semiconductor region to the third semiconductor region and the second semiconductor region. The trench penetrates the third semiconductor region, and the depth of the trench is shorter than that of a deepest bottom portion of the second semiconductor region, and the second semiconductor region does not exist under a bottom surface of the trench. A gate insulating film is formed on facing side surfaces of the trench. First and second gate electrodes are formed on the gate insulating film. The first and second gate electrodes are separated from each other. The conductive material is formed between the first and second gate electrodes on the side surfaces of the trench, with an insulating film intervened therebetween.
摘要翻译：在第一半导体区域上形成第二半导体区域。在第二半导体区域的一部分上形成第三半导体区域。沟槽的范围从第三半导体区域的表面到第三半导体区域和第二半导体区域。沟槽穿透第三半导体区域，并且沟槽的深度比第二半导体区域的最深底部的深度短，并且第二半导体区域不存在于沟槽的底表面之下。栅极绝缘膜形成在沟槽的相对的侧表面上。在栅极绝缘膜上形成第一和第二栅电极。第一和第二栅电极彼此分离。导电材料形成在沟槽的侧表面上的第一和第二栅电极之间，绝缘膜介于其间。

35. 发明申请

US20070034894A1 Semiconductor device including field effect transistor for use as a high-speed switching device and a power device 失效
标题翻译：包括用作高速开关装置的场效应晶体管和功率器件的半导体装置
公开(公告)号：US20070034894A1
公开(公告)日：2007-02-15
申请号：US11501715
申请日：2006-08-10
申请人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
发明人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
IPC分类号： H01L29/74
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.
摘要翻译：在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。在栅极绝缘膜上形成栅电极。偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

36. 发明申请

US20060157778A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060157778A1
公开(公告)日：2006-07-20
申请号：US11305202
申请日：2005-12-19
申请人： Syotaro Ono , Yusuke Kawaguchi , Yoshihiro Yamaguchi , Hirobumi Matsuki , Kiyotaka Arai
发明人： Syotaro Ono , Yusuke Kawaguchi , Yoshihiro Yamaguchi , Hirobumi Matsuki , Kiyotaka Arai
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0696
摘要： A power MOSFET includes an n-type drift layer and a p-type base layer formed in a layered manner on the n-type drift layer. Trench gates are formed to penetrate the p-type base layer to reach the n-type drift layer. On the p-type base layer, n+-type source regions and p+-type regions are formed. These n+-type source regions and p+-type regions are arranged alternately along a longitudinal direction of the trench gates. The n+-type source regions and the p+-type regions are arranged with a slant with respect to the longitudinal direction of the trench gates.
摘要翻译：功率MOSFET包括在n型漂移层上分层形成的n型漂移层和p型基极层。形成沟槽栅极以穿透p型基极层以到达n型漂移层。在p型基底层上形成n + +型源区和p + + +型区。这些n + + +型源极区域和p + + +区域沿沟槽栅极的纵向方向交替布置。相对于沟槽栅极的纵向方向，n + P +型源极区域和p + H +型区域以倾斜的方式排列。

37. 发明授权

US07067876B2 Semiconductor device 失效
公开(公告)号：US07067876B2
公开(公告)日：2006-06-27
申请号：US10139324
申请日：2002-05-07
申请人： Norio Yasuhara , Kazutoshi Nakamura , Yusuke Kawaguchi
发明人： Norio Yasuhara , Kazutoshi Nakamura , Yusuke Kawaguchi
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0696 , H01L29/1045 , H01L29/1087 , H01L29/4175 , H01L29/41766 , H01L29/4238
摘要： A semiconductor device comprises a semiconductor substrate; a semiconductor layer having a higher resistance than that of said semiconductor substrate and provided on a top surface of said semiconductor substrate; a gate electrode provided on a gate insulating film on the top surface of said semiconductor layer; a drain layer of a first conductivity type selectively provided in a location in said semiconductor layer in one side of said gate electrode; a drain electrode connected to said drain layer; a source layer of the first conductivity type selectively provided in a location in said semiconductor layer in the other side of said gate electrode; an element-side connecting portion selectively provided on said semiconductor layer, which does not reach a channel portion between said source layer and said drain layer of said semiconductor layer and also does not reach to said semiconductor substrate, and which is in contact with said source layer and has lower resistance than that of said semiconductor layer; a contact-side connecting portion selectively provided on said semiconductor layer, having lower resistance than said semiconductor layer and extending deeper toward said semiconductor substrate than said element-side connecting portion; a first source electrode connecting said source layer, said element-side connect portion and said contact-side connect portion; and a bottom electrode provided on the bottom surface of said semiconductor substrate in connection therewith.

38. 发明申请

US20060108590A1 Group III-V nitride series semiconductor substrate and assessment method therefor 有权
标题翻译： III-V族氮化物系半导体衬底及其评估方法
公开(公告)号：US20060108590A1
公开(公告)日：2006-05-25
申请号：US11033469
申请日：2005-01-12
申请人： Yusuke Kawaguchi
发明人： Yusuke Kawaguchi
IPC分类号： H01L33/00 , H01L31/12 , H01L27/15 , H01L29/26
CPC分类号： G01N21/6489 , H01L21/02389 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L21/0262 , H01L33/0075
摘要： The group III-V nitride series semiconductor substrate has good-product yield when the band-edge peak light-emission intensity ratio α=N1/N2 is α
摘要翻译：当带边峰值发光强度比α= N 1 / N 2时，III-V族氮化物系半导体衬底具有良好的产品产量，为α<1 其中N 1是在基板正面的任意光致发光测量位置处的带边峰值发光强度，N 2是带边缘峰值发光强度对应于光致发光测量位置的衬底背面的峰值发光强度。

39. 发明授权

US07026214B2 Offset-gate-type semiconductor device 失效
公开(公告)号：US07026214B2
公开(公告)日：2006-04-11
申请号：US10957692
申请日：2004-10-05
申请人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
发明人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L21/00
CPC分类号： H01L29/402 , H01L21/26586 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

40. 发明授权

US08395204B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08395204B2
公开(公告)日：2013-03-12
申请号：US13233993
申请日：2011-09-15
申请人： Yusuke Kawaguchi
发明人： Yusuke Kawaguchi
IPC分类号： H01L29/788
CPC分类号： H01L29/7813 , H01L29/0626 , H01L29/0696 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/7805 , H01L29/7808
摘要： According to one embodiment, a semiconductor device, includes an element unit including a vertical-type MOSFET, the vertical-type MOSFET in including a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer sequentially stacked in order, an impurity concentration of the second semiconductor layer being lower than the first semiconductor layer, an insulator covering inner surfaces of a plurality of trenches, the adjacent trenches being provided with a first interval in between, and a diode unit including basically with the units of the element unit, the adjacent trenches being provided with a second interval in between, the second interval being larger than the first interval.
摘要翻译：根据一个实施例，半导体器件包括包括垂直型MOSFET的元件单元，包括第一半导体层的垂直型MOSFET，第二半导体层，第三半导体层，第四半导体层，第五半导体层层，所述第二半导体层的杂质浓度低于所述第一半导体层，绝缘体覆盖多个沟槽的内表面，所述相邻沟槽之间设置有第一间隔，二极管单元包括：基本上与元件单元的单元相邻，相邻沟槽之间设置有第二间隔，第二间隔大于第一间隔。

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