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31. 发明授权

US07348616B2 Ferroelectric integrated circuit devices having an oxygen penetration path 失效
标题翻译：具有氧气穿透路径的铁电集成电路器件
公开(公告)号：US07348616B2
公开(公告)日：2008-03-25
申请号：US11248629
申请日：2005-10-12
申请人： Heung-jin Joo , Ki-nam Kim , Yoon-jong Song
发明人： Heung-jin Joo , Ki-nam Kim , Yoon-jong Song
IPC分类号： H01L29/76
CPC分类号： H01L28/55 , H01L27/11502 , H01L27/11507 , H01L28/57
摘要： Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.
摘要翻译：诸如存储器件的铁电集成电路器件形成在集成电路衬底上。铁电电容器在集成电路衬底上，并且集成电路衬底上的另一结构覆盖至少一部分铁电电容器。所述另外的结构包括至少一层，以提供对所述铁电电容器的氧气流的阻挡。与强电介质电容器接触的氧气穿透路径介于铁电电容器和另外的结构之间。提供氧流阻挡的层可以是封装的阻挡层。还提供了用于形成诸如存储器件的铁电集成电路器件的方法。

32. 发明申请

US20080070344A1 PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same 有权
标题翻译： PRAMS具有顺序地定位的多个活性区域和形成该活性区域的方法
公开(公告)号：US20080070344A1
公开(公告)日：2008-03-20
申请号：US11982940
申请日：2007-11-06
申请人： Jae-Hyun Park , Hyeong-Geun An , Su-Jin Ahn , Yoon-Jong Song , Hyung-Joo Youn , Kyu-Chul Kim
发明人： Jae-Hyun Park , Hyeong-Geun An , Su-Jin Ahn , Yoon-Jong Song , Hyung-Joo Youn , Kyu-Chul Kim
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/144
摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.
摘要翻译：提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。其他半导体衬底分别限定其它有源区。在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。

33. 发明申请

US20070272950A1 SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070272950A1
公开(公告)日：2007-11-29
申请号：US11753291
申请日：2007-05-24
申请人： Rak-Hwan KIM , Kyung-Chang RYOO , In-Sun PARK , Yoon-Jong SONG , Hyeon-Deok LEE , Hyun-Seok LIM
发明人： Rak-Hwan KIM , Kyung-Chang RYOO , In-Sun PARK , Yoon-Jong SONG , Hyeon-Deok LEE , Hyun-Seok LIM
IPC分类号： H01L27/10
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/1666
摘要： A method of fabricating a semiconductor memory device includes forming a first insulating layer and a sacrificial layer on a substrate. The first insulating layer and the sacrificial layer have an opening therein. A first conductive layer is formed in the opening and on the sacrificial layer. A second insulating layer is formed on the first conductive layer. The second insulating layer, the first conductive layer and the sacrificial layer are then planarized until the first insulating layer is exposed, thereby forming a first conductive pattern and a second insulating layer pattern in the opening. A phase change material layer is formed on the first conductive pattern, the first insulating layer and the second insulating layer pattern. A second conductive pattern is formed on the phase change material layer. A semiconductor memory device and a data processing system adopting the semiconductor memory device are also provided.
摘要翻译：制造半导体存储器件的方法包括在衬底上形成第一绝缘层和牺牲层。第一绝缘层和牺牲层在其中具有开口。在开口和牺牲层上形成第一导电层。在第一导电层上形成第二绝缘层。然后将第二绝缘层，第一导电层和牺牲层平坦化直到第一绝缘层露出，从而在开口中形成第一导电图案和第二绝缘层图案。在第一导电图案，第一绝缘层和第二绝缘层图案上形成相变材料层。在相变材料层上形成第二导电图案。还提供了半导体存储器件和采用半导体存储器件的数据处理系统。

34. 发明授权

US06979881B2 Ferroelectric integrated circuit devices having an oxygen penetration path 失效
标题翻译：具有氧气穿透路径的铁电集成电路器件
公开(公告)号：US06979881B2
公开(公告)日：2005-12-27
申请号：US10308843
申请日：2002-12-03
申请人： Heung-jin Joo , Ki-nam Kim , Yoon-jong Song
发明人： Heung-jin Joo , Ki-nam Kim , Yoon-jong Song
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8246 , H01L27/115 , H01L29/92
CPC分类号： H01L28/55 , H01L27/11502 , H01L27/11507 , H01L28/57
摘要： Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the Ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.
摘要翻译：诸如存储器件的铁电集成电路器件形成在集成电路衬底上。铁电电容器在集成电路基板上，并且集成电路基板上的另外的结构覆盖在铁电电容器的至少一部分上。所述另外的结构包括至少一层，以提供对所述铁电电容器的氧气流的阻挡。与强电介质电容器接触的氧气穿透路径介于铁电电容器和另外的结构之间。提供氧流阻挡的层可以是封装的阻挡层。还提供了用于形成诸如存储器件的铁电集成电路器件的方法。

35. 发明授权

US06956279B2 Semiconductor device having multi-layer oxygen barrier pattern 失效
标题翻译：具有多层氧阻挡图案的半导体器件
公开(公告)号：US06956279B2
公开(公告)日：2005-10-18
申请号：US09956498
申请日：2001-09-18
申请人： Yoon-Jong Song
发明人： Yoon-Jong Song
IPC分类号： H01L27/105 , H01L21/02 , H01L21/285 , H01L21/8246 , H01L27/115 , H01L29/92 , H01L27/108
CPC分类号： H01L27/11502 , H01L21/28568 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： The present invention relates to the field of a semiconductor device having a ferroelectric material capacitor and method of making the same. The semiconductor device includes a capacitor having a triple-level oxygen barrier layer pattern formed by an oxygen barrier metal layer, a material layer formed of a conductive solid solution by compounding the oxygen barrier metal layer and oxygen, and an oxygen barrier metal on an interlayer dielectric with a contact plug. The capacitor also has an electrode and a ferroelectric film electrically contacting to the oxygen barrier layer. Further, a wetting layer is formed between the oxygen barrier layer and the contact plug, and an iridium oxygen layer is formed between the oxygen barrier layer and a capacitor electrode.
摘要翻译：本发明涉及具有铁电材料电容器的半导体器件的领域及其制造方法。该半导体器件包括具有由氧阻隔金属层形成的三层氧阻隔层图案的电容器，通过将氧阻隔金属层与氧混合而形成的导电固溶体的材料层和中间层上的阻氧金属电介质与接触塞。电容器还具有与氧阻隔层电接触的电极和铁电体膜。此外，在氧阻隔层和接触塞之间形成润湿层，并且在氧阻隔层和电容器电极之间形成铱氧层。

36. 发明授权

US06825082B2 Ferroelectric memory device and method of forming the same 失效
标题翻译：铁电存储器件及其形成方法
公开(公告)号：US06825082B2
公开(公告)日：2004-11-30
申请号：US10800273
申请日：2004-03-11
申请人： Ki-Nam Kim , Yoon-Jong Song
发明人： Ki-Nam Kim , Yoon-Jong Song
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L21/3144 , H01L21/3185 , H01L21/76895 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： A ferroelectric memory device along with a method of forming the same are provided. A first interlayer insulating layer is formed on a semiconductor substrate. A buried contact structure is formed on the first interlayer insulating layer. The buried contact structure is electrically connected to the substrate through a first contact hole extending through the first interlayer insulating layer. A blocking layer covers or encapsulates the buried contact structure and the first interlayer insulating layer. A second interlayer insulating layer is formed on the blocking layer. A ferroelectric capacitor formed on the second interlayer insulating layer and is electrically connected to the buried contact structure through a second contact hole that penetrates the second interlayer insulating layer and the blocking layer.
摘要翻译：提供了一种铁电存储器件及其形成方法。第一层间绝缘层形成在半导体衬底上。在第一层间绝缘层上形成掩埋接触结构。掩埋接触结构通过延伸穿过第一层间绝缘层的第一接触孔电连接至基板。阻挡层覆盖或封装埋层接触结构和第一层间绝缘层。在阻挡层上形成第二层间绝缘层。形成在所述第二层间绝缘层上的铁电电容器，其通过贯穿所述第二层间绝缘层和所述阻挡层的第二接触孔与所述埋入触点结构电连接。

37. 发明授权

US06713310B2 Ferroelectric memory device using via etch-stop layer and method for manufacturing the same 失效
公开(公告)号：US06713310B2
公开(公告)日：2004-03-30
申请号：US10354651
申请日：2003-01-29
申请人： Yoon-Jong Song , Ki-Nam Kim , Sang-Woo Lee
发明人： Yoon-Jong Song , Ki-Nam Kim , Sang-Woo Lee
IPC分类号： H01G706
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A ferroelectric memory device and a method for manufacturing the same. The ferroelectric memory device comprises a lower interlayer insulating layer formed on a semiconductor substrate. The ferroelectric memory device further comprises at least two adjacent ferroelectric capacitors disposed on the lower interlayer insulating layer, an interlayer insulation layer formed over the ferroelectric capacitors, leaving a top surface of the ferroelectric capacitors exposed, a patterned via etch-stop layer formed on the interlayer insulation layer, leaving the top surface of the capacitors exposed, an upper interlayer insulating layer formed on the patterned via etch-stop layer, and a plate line commonly connected to the at least two adjacent ferroelectric capacitors. Thus, integration of the ferroelectric memory device can be substantially increased.

38. 发明申请

US20170069684A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：磁性随机访问存储器件及其制造方法
公开(公告)号：US20170069684A1
公开(公告)日：2017-03-09
申请号：US15157403
申请日：2016-05-17
申请人： Ki-Seok SUH , Jae-Chul SHIM , Kil-Ho LEE , Yong-Seok CHUNG , Gwan-Hyeob KOH , Yoon-Jong SONG
发明人： Ki-Seok SUH , Jae-Chul SHIM , Kil-Ho LEE , Yong-Seok CHUNG , Gwan-Hyeob KOH , Yoon-Jong SONG
IPC分类号： H01L27/22 , H01L43/02 , H01L43/10 , H01L43/12
CPC分类号： H01L27/222 , H01L43/12
摘要： A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.
摘要翻译：制造MRAM器件的方法包括在衬底上依次形成第一绝缘层和蚀刻停止层。通过蚀刻停止层和第一绝缘中间层形成下电极。在下电极和蚀刻停止层上依次形成MTJ结构层和上电极。通过使用上电极作为蚀刻掩模的物理蚀刻工艺对MTJ结构层进行构图，以形成至少部分地接触下电极的MTJ结构。第一绝缘中间层由蚀刻停止层保护，因此不被物理蚀刻工艺蚀刻。

39. 发明授权

US08203135B2 Semiconductor device including uniform contact plugs and a method of manufacturing the same 有权
标题翻译：包括均匀接触塞的半导体器件及其制造方法
公开(公告)号：US08203135B2
公开(公告)日：2012-06-19
申请号：US12697620
申请日：2010-02-01
申请人： Kyu-Rie Sim , Jung-Hoon Park , Yoon-Jong Song , Jae-Min Shin , Shin-Hee Han
发明人： Kyu-Rie Sim , Jung-Hoon Park , Yoon-Jong Song , Jae-Min Shin , Shin-Hee Han
IPC分类号： H01L29/41
CPC分类号： H01L27/24 , H01L27/222
摘要： A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another. The semiconductor device further includes a plurality of electrode patterns conformably formed on the inside of the sidewall patterns and having size errors less than 10%, and a plurality of filling patterns formed inside the electrode patterns and completely filling the inside of the contact holes.
摘要翻译：提供半导体器件，半导体模块，电子设备及其制造和制造方法。半导体器件包括形成在衬底上的下互连，形成在下互连上的多个控制图案，形成在控制图案上的多个下接触插塞图案，形成在下接触插塞图案上的多个存储图案，形成在存储图案上的多个上电极和形成在上电极上的多个上互连。下接触插头图案各自包括具有不同尺寸的至少两个接触孔，多个侧壁图案形成在两个接触孔的内侧壁上，并且其中侧壁图案具有彼此不同的厚度。半导体器件还包括多个沿着侧壁图案的内侧形成并且具有小于10％的尺寸误差的电极图案，以及形成在电极图案内并且完全填充接触孔内部的多个填充图案。

40. 发明授权

US08129214B2 Phase change memory devices having dual lower electrodes and methods of fabricating the same 有权
标题翻译：具有双下电极的相变存储器件及其制造方法
公开(公告)号：US08129214B2
公开(公告)日：2012-03-06
申请号：US12709536
申请日：2010-02-22
申请人： Yoon-Jong Song , Kyung-Chang Ryoo , Dong-Won Lim
发明人： Yoon-Jong Song , Kyung-Chang Ryoo , Dong-Won Lim
IPC分类号： H01L21/00 , H01L45/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/1675
摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.
摘要翻译：半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。包括通过下层间绝缘层并露出衬底的开口。掩埋绝缘图案设置在开口中。依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。还提供了制造半导体器件的方法。

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