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31. 发明授权

US06570212B1 Complementary avalanche injection EEPROM cell 失效
标题翻译：互补雪崩注入EEPROM单元
公开(公告)号：US06570212B1
公开(公告)日：2003-05-27
申请号：US09578086
申请日：2000-05-24
申请人： Sunil D. Mehta , Steven Fong , Stewart Logie
发明人： Sunil D. Mehta , Steven Fong , Stewart Logie
IPC分类号： H01L27108
CPC分类号： H01L27/11526 , G11C16/0441 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11529 , H01L27/11558 , H01L29/66825
摘要： A non-volatile memory cell at least partially formed in a semiconductor substrate, comprising a first avalanche injection element having a first active region of a first conductivity type and a second active region of a second conductivity type, separated by a channel region of said second conductivity type; a second avalanche injection element having a third active region of said second conductivity type and sharing said second active region with said first avalanche injection element, the second avalanche injection element having a channel region of said first conductivity type; and a common floating gate at least partially overlying said first and second avalanche injection elements. In a further embodiment, the first avalanche element has an N+/P junction, the second avalanche element has a P+/N junction, and the floating gate capacitively coupled to the first and second avalanche elements.
摘要翻译：至少部分地形成在半导体衬底中的非易失性存储单元，包括具有第一导电类型的第一有源区和第二导电类型的第二有源区的第一雪崩注入元件，由所述第二导电类型的沟道区分隔开导电型; 第二雪崩注入元件，具有所述第二导电类型的第三有源区，并且与所述第一雪崩注入元件共享所述第二有源区，所述第二雪崩注入元件具有所述第一导电类型的沟道区; 以及至少部分地覆盖所述第一和第二雪崩注入元件的公共浮动栅极。在另一实施例中，第一雪崩元件具有N + / P结，第二雪崩元件具有P + / N结，并且浮动栅极电容耦合到第一和第二雪崩元件。

32. 发明授权

US06424003B1 EEPROM cell with self-aligned tunneling window 有权
公开(公告)号：US06424003B1
公开(公告)日：2002-07-23
申请号：US09169492
申请日：1998-10-09
申请人： Xiao Yu Li , Sunil D. Mehta , Christopher O. Schmidt
发明人： Xiao Yu Li , Sunil D. Mehta , Christopher O. Schmidt
IPC分类号： H07L29788
摘要： An improved EEPROM cell with a self-aligned tunneling window is provided which is fabricated by a standard STI process so as to produce a smaller layout size and a reduced cell height. The EEPROM cell includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The length dimension of the floating gate is less than the length dimension of the tunneling window so that the tunneling window is overlapping the floating gate. The tunneling window is self-aligned by edges forming the length dimension of the floating gate so as to form a self-aligned tunneling window.

33. 发明授权

US06362527B1 Borderless vias on bottom metal 失效
标题翻译：底部金属上的无边界通道
公开(公告)号：US06362527B1
公开(公告)日：2002-03-26
申请号：US08754564
申请日：1996-11-21
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： H01L2348
CPC分类号： H01L21/76897 , H01L21/76819 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An improved manufacturing process and an improved device made by the process for forming via interconnects between metal layers in a multilevel metallization structure substantially eliminates trench formation during via overetch and exploding vias during via fill. An insulating multilayer structure comprising a conformal oxide, a spin-on layer, and an etch stop layer for the via etch locally planarizes the region adjacent to metal lines before the ILD is deposited and vias are patterned and etched. Using this process, metal borders around vias can be reduced or eliminated, thereby increasing circuit packing density.
摘要翻译：通过用于在多层金属化结构中的金属层之间经由互连形成的工艺制造的改进的制造工艺和改进的装置基本上消除了通孔过孔期间的沟槽形成和在通孔填充过程中爆炸通孔。包含保形氧化物，旋涂层和用于通孔蚀刻的蚀刻停止层的绝缘多层结构在淀积ILD之前将与金属线相邻的区域平面化，并对通孔进行图案化和蚀刻。使用该工艺可以减少或消除通孔周围的金属边界，从而增加电路封装密度。

34. 发明授权

US06326663B1 Avalanche injection EEPROM memory cell with P-type control gate 失效
标题翻译：雪崩注入EEPROM存储单元，带P型控制门
公开(公告)号：US06326663B1
公开(公告)日：2001-12-04
申请号：US09277441
申请日：1999-03-26
申请人： Xiao-Yu Li , Steven J. Fong , Sunil D. Mehta
发明人： Xiao-Yu Li , Steven J. Fong , Sunil D. Mehta
IPC分类号： H01L29788
CPC分类号： H01L27/11517 , H01L27/115
摘要： A non-volatile memory cell, comprising a semiconductor substrate having a first conductivity type. A control region is formed of said first conductivity type in the substrate and a control region oxide formed over the control region. The cell includes a program element having a first active region of a second conductivity type formed in said substrate, a doped or implanted region adjacent to said first active region, and a gate oxide overlying at least the channel region. An active region oxide covers a portion of the first active region. A floating gate is formed over said semiconductor substrate on said active region oxide and said control region oxide.
摘要翻译：一种非易失性存储单元，包括具有第一导电类型的半导体衬底。控制区域由衬底中的所述第一导电类型形成，并且在控制区域上形成控制区氧化物。单元包括具有形成在所述衬底中的第二导电类型的第一有源区，与所述第一有源区相邻的掺杂或注入区以及覆盖至少沟道区的栅极氧化物的程序元件。有源区氧化物覆盖第一有源区的一部分。在所述有源区氧化物和所述控制区氧化物上的所述半导体衬底上形成浮栅。

35. 发明授权

US06232631B1 Floating gate memory cell structure with programming mechanism outside the read path 失效
标题翻译：浮动门存储单元结构，具有读取路径外的编程机制
公开(公告)号：US06232631B1
公开(公告)日：2001-05-15
申请号：US09217648
申请日：1998-12-21
申请人： Christopher O. Schmidt , Sunil D. Mehta
发明人： Christopher O. Schmidt , Sunil D. Mehta
IPC分类号： H01L29788
CPC分类号： G11C16/0441 , H01L27/115
摘要： A non-volatile memory cell structure includes a floating gate, a reverse breakdown hot carrier injection element and a sense transistor. The reverse breakdown hot carrier injection element is at least partially formed in a first region of a semiconductor substrate under at least a portion of the floating gate. The sense transistor is at least partially formed in a second region of a semiconductor substrate, isolated from the first region, and under at least a portion of the floating gate. A read transistor may be connected to the sense transistor. In one embodiment, the read transistor is at least partially formed in the second region of a semiconductor substrate, and connected to the sense transistor.
摘要翻译：非易失性存储单元结构包括浮置栅极，反向击穿热载流子注入元件和感测晶体管。反向击穿热载流子注入元件至少部分地形成在半导体衬底的至少一部分浮动栅极的第一区域内。感测晶体管至少部分地形成在半导体衬底的与第一区域隔离的第二区域中，并且至少部分地形成在浮置栅极的至少一部分下方。读取晶体管可以连接到感测晶体管。在一个实施例中，读取晶体管至少部分地形成在半导体衬底的第二区域中，并连接到感测晶体管。

36. 发明授权

US6166428A Formation of a barrier layer for tungsten damascene interconnects by nitrogen implantation of amorphous silicon or polysilicon 失效
标题翻译：通过非晶硅或多晶硅的氮注入形成钨镶嵌互连的阻挡层
公开(公告)号：US6166428A
公开(公告)日：2000-12-26
申请号：US917153
申请日：1997-08-25
申请人： Sunil D. Mehta , William G. En , Darin Arthur Chan , Raymond Takling Lee
发明人： Sunil D. Mehta , William G. En , Darin Arthur Chan , Raymond Takling Lee
IPC分类号： H01L21/28 , H01L21/768 , H01L23/26 , H01L23/58
CPC分类号： H01L21/28273 , H01L21/76825 , H01L21/76832 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L23/26 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor device having at least a first and second type of devices formed in the substrate of the semiconductor device and having a hydrogen free barrier layer formed by implanting nitrogen into a layer of amorphous silicon or polysilicon formed on the surface of the semiconductor device. A hydrogen getter layer is formed on the semiconductor device under the barrier layer. The hydrogen getter layer is removed from portions of the semiconductor device on which salicide layers are to be formed.
摘要翻译：一种半导体器件，其具有形成在半导体器件的衬底中的至少第一和第二类型的器件，并具有通过将氮注入形成在半导体器件的表面上的非晶硅层或多晶硅层而形成的无氢阻挡层。在阻挡层下的半导体器件上形成吸氢剂层。从半导体器件的要形成硅化物层的部分去除吸氢剂层。

37. 发明授权

US06093946A EEPROM cell with field-edgeless tunnel window using shallow trench isolation process 失效
标题翻译：具有无源隧道窗的EEPROM单元采用浅沟槽隔离工艺
公开(公告)号：US06093946A
公开(公告)日：2000-07-25
申请号：US26814
申请日：1998-02-20
申请人： Xiao-Yu Li , Sunil D. Mehta
发明人： Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/7883
摘要： An improved EEPROM cell having a field-edgeless tunnel window is provided which is fabricated by a STI process so as to produce reliable endurance and data retention. The EEPROM cell includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The tunneling oxide layer defines a tunnel window which allows for programming and erasing of the floating gate by tunneling electrons therethrough. The programmable junction region has a width dimension and a length dimension so as to define a first area. The tunnel window has a width dimension and a length dimension so as to define a second area. The second area of the tunnel window is completely confined within the first area of the programmable junction region so as to form a field-edgeless tunnel window.
摘要翻译：提供了具有场无边界隧道窗的改进的EEPROM单元，其通过STI工艺制造，以便产生可靠的耐久性和数据保持。 EEPROM单元包括浮置栅极，可编程结区域和分离可编程结区域和浮置栅极的隧穿氧化物层。隧道氧化物层限定隧道窗口，其允许通过隧穿电子进行浮动栅极的编程和擦除。可编程连接区域具有宽度尺寸和长度尺寸，以便限定第一区域。隧道窗口具有宽度尺寸和长度尺寸，以便限定第二区域。隧道窗口的第二区域被完全限制在可编程连接区域的第一区域内，从而形成无边界的隧道窗口。

38. 发明授权

US6087696A Stacked tunneling dielectric technology for improving data retention of EEPROM cell 失效
标题翻译：堆叠隧道电介质技术，用于改善EEPROM单元的数据保留
公开(公告)号：US6087696A
公开(公告)日：2000-07-11
申请号：US86437
申请日：1998-05-28
申请人： Xiao-Yu Li , Qi Xiang , Sunil D. Mehta
发明人： Xiao-Yu Li , Qi Xiang , Sunil D. Mehta
IPC分类号： H01L21/28 , H01L21/8247 , H01L29/51 , H01L29/788
CPC分类号： H01L21/28194 , H01L21/28273 , H01L27/11521 , H01L27/11558 , H01L29/513 , H01L29/517 , H01L21/28202 , H01L21/28211 , H01L29/518
摘要： An improved EEPROM cell structure and a method of fabricating the same is provided so as to improve data retention. The EEPROM cell includes a stacked dielectric structure consisting of a thin tunnel oxide layer and a high-k dielectric layer to function as the tunneling dielectric barrier so as to suppress leakage current.
摘要翻译：提供了改进的EEPROM单元结构及其制造方法，以便改善数据保留。 EEPROM单元包括由薄的隧道氧化物层和高k电介质层构成的叠层电介质结构，用作隧道电介质势垒，以便抑制漏电流。

39. 发明授权

US6034893A Non-volatile memory cell having dual avalanche injection elements 有权
标题翻译：具有双雪崩注入元件的非易失性存储单元
公开(公告)号：US6034893A
公开(公告)日：2000-03-07
申请号：US334052
申请日：1999-06-15
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： G11C16/04 , H01L21/8247 , H01L29/861
CPC分类号： H01L29/8616 , G11C16/0441 , H01L27/11521 , H01L27/11558
摘要： A non-volatile memory cell includes a well region formed in a semiconductor substrate. First and second avalanche injection elements reside in the well region. A bifurcated floating-gate electrode includes a first segment overlying the first avalanche injection element and a second segment overlying the second avalanche injection element. A first contact region resides in the well region adjacent to the first segment of the floating-gate electrode, and a second contact region resides in the well region adjacent to the second segment of the floating-gate electrode. Upon the application of programming or erasing voltage, electrical charge is independently transferred to each of the first and second segments of the floating-gate electrode from the first and second avalanche injection elements, respectively.
摘要翻译：非易失性存储单元包括形成在半导体衬底中的阱区。第一和第二雪崩注入元件驻留在井区域中。分叉浮栅电极包括覆盖第一雪崩注入元件的第一段和覆盖第二雪崩注入元件的第二段。第一接触区域位于与浮栅电极的第一段相邻的阱区中，并且第二接触区位于与浮栅电极的第二段相邻的阱区中。在施加编程或擦除电压时，电荷分别独立地从第一和第二雪崩注入元件转移到浮栅电极的第一和第二段中的每一个。

40. 发明授权

US6025637A Spacer-based antifuse structure for low capacitance and high reliability and method of fabrication thereof 失效
标题翻译：用于低电容和高可靠性的基于隔板的反熔丝结构及其制造方法
公开(公告)号：US6025637A
公开(公告)日：2000-02-15
申请号：US23669
申请日：1998-02-10
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： H01L21/82 , H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： The present antifuse includes a base having a first electrode thereon which defines a top surface and a side surface. Antifuse material is disposed on the first electrode on at least a portion of the top surface and at least a portion of the side surface, with a second electrode on the antifuse material. Due to this configuration, defect problems in etching oxide as part of the antifuse structure are avoided, and meanwhile capacitance of the device is very low.
摘要翻译：本发明的反熔丝包括其上具有限定顶表面和侧表面的第一电极的基座。防腐材料在顶表面的至少一部分和侧表面的至少一部分上设置在第一电极上，反熔丝材料上具有第二电极。由于该构造，避免了作为反熔丝结构的一部分的蚀刻氧化物中的缺陷问题，同时器件的电容非常低。

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