专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US6083795A Large angle channel threshold implant for improving reverse narrow width effect 失效
标题翻译：大角度通道阈值植入物，用于改善反向窄宽度效应
公开(公告)号：US6083795A
公开(公告)日：2000-07-04
申请号：US20497
申请日：1998-02-09
申请人： Mong-Song Liang , Ching-Hsiang Hsu
发明人： Mong-Song Liang , Ching-Hsiang Hsu
IPC分类号： H01L21/265 , H01L21/762 , H01L29/10 , H01L21/336 , H01L21/425
CPC分类号： H01L21/26586 , H01L21/76216 , H01L29/1033
摘要： The present invention provides a method of manufacturing MOS device having threshold voltage adjustment region 28 ormed using a large angled implant. The invention's angled implant serves as both (a) a Vt adjustment I/I and (b) a Channel stop I/I by (1) increasing the threshold voltage (Vt) and (2) reducing the leakage current. The method comprises forming spaced field oxide regions having bird's beaks on a semiconductor substrate. A field implant is performed using the spaced field oxide regions as an implant mask formed a deep channel stop region 24. Next, a sacrificial oxide layer 20 is formed over the resultant surface. In a critical step, a threshold voltage adjustment region 28 is formed by performing a large angled implant of a p-type ions. The p-type ions into are implanted into the channel region 19 and under the bird's beak 18 such that the threshold voltage is higher under the bird's beak than in the channel region 19. A MOS transistor is then formed over the channel region. The large angled threshold voltage implant of the present invention eliminates the reverse narrow width effect (e.g., reduced threshold voltage (Vt) and increased leakage currents).
摘要翻译：本发明提供了一种制造具有阈值电压调节区域28的MOS器件的方法，所述阈值电压调节区域28使用大角度植入物进行。本发明的倾斜注入用作（a）Vt调节I / I和（b）通道停止I / I，通过（1）增加阈值电压（Vt）和（2）减小漏电流。该方法包括在半导体衬底上形成具有鸟喙的间隔的场氧化物区域。使用间隔的场氧化物区域作为形成深沟道停止区域24的注入掩模来执行场注入。接下来，在所得表面上形成牺牲氧化物层20。在关键步骤中，通过执行p型离子的大角度注入来形成阈值电压调整区域28。将p型离子注入到通道区域19中并且在鸟的嘴部18下方，使得阈值电压在鸟喙下比通道区域19中更高。然后在沟道区域上形成MOS晶体管。本发明的大角度阈值电压注入消除了反向窄宽度效应（例如，降低的阈值电压（Vt）和增加的漏电流）。

32. 发明授权

US6001731A Isolation dielectric deposition in multi-polysilicon chemical-mechanical polishing process 失效
标题翻译：多晶硅化学机械抛光工艺中的隔离电介质沉积
公开(公告)号：US6001731A
公开(公告)日：1999-12-14
申请号：US682457
申请日：1996-07-17
申请人： Chung-Hui Su , Mong-Song Liang , Shou-Gwo Wuu , Chen-Jong Wang
发明人： Chung-Hui Su , Mong-Song Liang , Shou-Gwo Wuu , Chen-Jong Wang
IPC分类号： H01L21/3105 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76819 , H01L21/31053
摘要： A method for providing a chemical mechanical polishing planarization process for preventing multi-polysilicon and multi-metal level electrical shorts, which includes briefly the sequential processing steps of i) providing an insulating layer to a first thickness over a device wafer with non-planar surface topography; ii) chemical-mechanical polishing the first insulating layer; and iii) deposition of another polysilicon layer of second thickness to prevent the barely exposed or exposed underlying polysilicon from shorting to the next polysilicon or metal level of interconnects.
摘要翻译：一种用于提供用于防止多晶硅和多金属级电短路的化学机械抛光平面化工艺的方法，其中简要地描述了以下顺序的处理步骤：i）在具有非平面表面的器件晶片上提供第一厚度的绝缘层地形; ii）化学机械抛光第一绝缘层; 以及iii）沉积第二厚度的另一多晶硅层，以防止几乎暴露或暴露的下面的多晶硅短路到下一个多晶硅或金属互连级。

33. 发明授权

US5877523A Multi-level split- gate flash memory cell 失效
标题翻译：多级分闸闪存单元
公开(公告)号：US5877523A
公开(公告)日：1999-03-02
申请号：US974459
申请日：1997-11-20
申请人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
发明人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
IPC分类号： G11C11/56 , G11C16/04 , H01L21/28 , H01L21/336 , H01L29/788
CPC分类号： G11C16/0475 , G11C11/5621 , G11C16/0458 , H01L21/28273 , H01L29/66825 , H01L29/7887 , G11C2211/5612
摘要： A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes. There are source/drain regions in the substrate self-aligned with the control gate electrode.
摘要翻译：半导体存储器件形成在掺杂半导体衬底上，并被掺杂的第一多晶硅层依次覆盖的隧道氧化物层覆盖。将第一多晶硅层图案化成一对浮栅电极。电极间电介质层覆盖浮置栅电极，浮置栅电极的侧壁和隧道氧化物的边缘在浮栅电极下方。第二多晶硅层覆盖在电极之间的电介质层上，又由硅化钨层覆盖。第二介电层覆盖硅化钨层。跨越一对浮置栅电极的控制栅极电极由第二多晶硅层形成，硅化钨和第一和第二电介质层图案化成栅电极堆叠，提供横跨该对浮置栅电极的控制栅电极。衬底中的源极/漏极区域与控制栅电极自对准。

34. 发明授权

US5861634A Charge collector structure for detecting radiation induced charge during integrated circuit processing 失效
标题翻译：用于在集成电路处理期间检测辐射感应电荷的电荷收集器结构
公开(公告)号：US5861634A
公开(公告)日：1999-01-19
申请号：US871504
申请日：1997-06-09
申请人： Ching-Hsiang Hsu , Chrong-Jung Lin , Mong-Song Liang
发明人： Ching-Hsiang Hsu , Chrong-Jung Lin , Mong-Song Liang
IPC分类号： H01L23/544 , H01L23/58
CPC分类号： H01L22/34
摘要： A method and structure for the evaluation of the density of charge induced to a semiconductor substrate during exposure to radiation as a result of integrated circuits processing procedures such as ion implantation and plasma etching is disclosed. A plurality of stacked gate field effect transistors, wherein each stacked has a charge collection capacitor attached to the gate, is fabricated on a semiconductor substrate. Each charge collection capacitor has an area that is different from every other charge collection capacitor. The to substrate is exposed to a radiation source. The threshold voltage for each of the stacked gate field effect transistors is measured. The difference in threshold voltage for the stacked gate transistors is proportional to the amount of charge induced during the exposure to the radiation and the density of the charge induced by the exposure to the radiation can be calculated from the comparison of the threshold voltage and the area of the charge collection capacitors.
摘要翻译：公开了用于评价由于诸如离子注入和等离子体蚀刻的集成电路处理过程而在暴露于辐射期间对半导体衬底感生的电荷密度的评估方法和结构。在半导体衬底上制造多个堆叠栅极场效应晶体管，其中每个层叠有一个附着到栅极的电荷收集电容器。每个电荷收集电容器具有与每个其他电荷收集电容器不同的面积。将衬底暴露于辐射源。测量每个堆叠栅极场效应晶体管的阈值电压。堆叠栅极晶体管的阈值电压的差异与在曝光到辐射期间感应的电荷量成比例，并且可以从阈值电压和面积的比较来计算由暴露于辐射引起的电荷的密度的电荷收集电容器。

35. 发明授权

US5818085A Body contact for a MOSFET device fabricated in an SOI layer 失效
标题翻译：用于在SOI层中制造的MOSFET器件的体接触
公开(公告)号：US5818085A
公开(公告)日：1998-10-06
申请号：US892337
申请日：1997-07-14
申请人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
发明人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
IPC分类号： H01L21/336 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L29/78612 , H01L29/78621
摘要： A MOSFET device structure, on a silicon on insulator layer, in which a body contact to the silicon on insulator layer exists, has been developed. The MOSFET device structure features a heavily doped P type body contact region in a lightly doped source and drain region of the MOSFET device structure, formed from an ion implantation through a metal silicide layer. The addition of the body contact results in more controllable device characteristics, in terms of drain currents, etc., than for counterparts fabricated in silicon on insulator layer, without the use of a body contact.
摘要翻译：已经开发了在绝缘体上硅层上存在与绝缘体上硅层接触体的MOSFET器件结构。 MOSFET器件结构在MOSFET器件结构的轻掺杂源极和漏极区域中具有重掺杂的P型体接触区域，其通过金属硅化物层的离子注入形成。身体接触的添加导致在漏极电流等方面比在绝缘体层上制造的对应物更不可控的器件特性，而不使用身体接触。

36. 发明授权

US5801415A Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors 失效
标题翻译：用于具有沟槽状耦合电容器的电可编程只读存储器的非易失性存储单元
公开(公告)号：US5801415A
公开(公告)日：1998-09-01
申请号：US947832
申请日：1997-10-08
申请人： Jin-Yuan Lee , Mong-Song Liang
发明人： Jin-Yuan Lee , Mong-Song Liang
IPC分类号： H01L21/8247 , H01L29/423 , H01L29/788 , H01L29/76
CPC分类号： H01L27/11521 , H01L29/42324
摘要： A method for making an improved Electrically Programmable Read-Only-Memory (EPROM) device having non-volatile memory cells with enhanced capacitive coupling was achieved. The array of memory cells consists of a single field effect transistor (FET) having an additional floating gate. The FET is formed in a well etched into an insulating layer on the substrate surface. After forming the FET gate oxide, a polysilicon layer is patterned to form a trench-like floating gate with increased capacitive coupling. An interlevel dielectric layer is deposited. A second poly-silicon layer is deposited in the well and chem/mech polished back to form the control gate. The insulating layer having the wells is selectively removed. Lightly doped source/drain areas, self-aligned to the FET gate electrodes, are implanted and after forming sidewall spacers on the gate electrodes, source/drain contacts and buried bit lines are formed by a second implant. An insulating layer is deposited over the array of FETs having contact openings to the FET control gates. Another polysilicon layer is deposited and patterned to form the word lines. The word lines and buried bit lines are connected to the peripheral circuits to complete the EPROM chip.
摘要翻译：实现了具有增强的电容耦合的具有非易失性存储单元的改进的可编程只读存储器（EPROM）装置的方法。存储器单元的阵列由具有附加浮置栅极的单个场效应晶体管（FET）组成。 FET被形成在衬底表面上被很好地刻蚀成绝缘层的阱中。在形成FET栅极氧化物之后，将多晶硅层图案化以形成具有增加的电容耦合的沟槽状浮栅。沉积层间电介质层。第二个多晶硅层沉积在阱中，化学/机械表面抛光后形成控制栅极。选择性地除去具有孔的绝缘层。注入与FET栅电极自对准的轻掺杂源极/漏极区，并且在栅电极上形成侧壁间隔物之后，通过第二植入物形成源极/漏极接触和掩埋位线。绝缘层沉积在具有与FET控制栅极的接触开口的FET阵列上。沉积并图案化另一个多晶硅层以形成字线。字线和掩埋位线连接到外围电路以完成EPROM芯片。

37. 发明授权

US5714412A Multi-level, split-gate, flash memory cell and method of manufacture thereof 失效
标题翻译：多级，分裂门，闪存单元及其制造方法
公开(公告)号：US5714412A
公开(公告)日：1998-02-03
申请号：US755868
申请日：1996-12-02
申请人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
发明人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
IPC分类号： G11C11/56 , G11C16/04 , H01L21/28 , H01L21/336 , H01L29/788 , H01L21/8247
CPC分类号： G11C16/0475 , G11C11/5621 , G11C16/0458 , H01L21/28273 , H01L29/66825 , H01L29/7887 , G11C2211/5612
摘要： A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes. There are source/drain regions in the substrate self-aligned with the control gate electrode.
摘要翻译：半导体存储器件形成在掺杂半导体衬底上，并被掺杂的第一多晶硅层依次覆盖的隧道氧化物层覆盖。将第一多晶硅层图案化成一对浮栅电极。电极间电介质层覆盖浮置栅电极，浮置栅电极的侧壁和隧道氧化物的边缘在浮栅电极下方。第二多晶硅层覆盖在电极之间的电介质层上，又由硅化钨层覆盖。第二介电层覆盖硅化钨层。跨越一对浮置栅电极的控制栅极电极由第二多晶硅层形成，硅化钨和第一和第二电介质层图案化成栅电极堆叠，提供横跨该对浮置栅电极的控制栅电极。衬底中的源极/漏极区域与控制栅电极自对准。

38. 发明授权

US5654231A Method of eliminating buried contact trench in SRAM technology 失效
标题翻译：在SRAM技术中消除埋接触沟的方法
公开(公告)号：US5654231A
公开(公告)日：1997-08-05
申请号：US621273
申请日：1996-03-25
申请人： Mong-Song Liang , Jin-Yuan Lee , Chun-Yi Shih
发明人： Mong-Song Liang , Jin-Yuan Lee , Chun-Yi Shih
IPC分类号： H01L21/28 , H01L21/8244
CPC分类号： H01L27/11 , H01L21/28
摘要： A new method of forming an improved buried contact junction is described. A first polysilicon layer is deposited overlying a gate silicon oxide layer on the surface of a semiconductor substrate. The first polysilicon and gate oxide layers are etched away where they are not covered by a buried contact mask to provide an opening to the semiconductor substrate. Ions are implanted through the opening into the semiconductor substrate to form a buried contact junction. A layer of dielectric material is deposited over the first polysilicon layer and over the semiconductor substrate within the opening. The layer is anisotropically etched to leave spacers on the sidewalls of the first polysilicon layer and adjacent the opening. A second layer of polysilicon is deposited overlying the first polysilicon layer and over the substrate within the opening. The second polysilicon layer is patterned to form gate electrodes and a polysilicon contact overlying the buried contact junction wherein the mask used for the patterning is misaligned and a portion of a spacer overlying the buried contact junction is exposed and wherein a portion of the second polysilicon layer other than that of the contact remains as residue. The second polysilicon layer residue is etched away wherein the exposed spacer protects the buried contact junction within the semiconductor substrate from the etching to complete the formation of a buried contact in the fabrication of an integrated circuit.
摘要翻译：描述了形成改进的埋地接触结的新方法。沉积在半导体衬底的表面上的栅极氧化硅层上的第一多晶硅层。第一多晶硅和栅极氧化物层被蚀刻掉，其中它们不被掩埋的接触掩模覆盖以提供到半导体衬底的开口。离子通过开口植入半导体衬底中以形成掩埋接触结。电介质材料层沉积在开口内的第一多晶硅层上方和半导体衬底之上。该层被各向异性地蚀刻以在第一多晶硅层的侧壁和邻近开口处留下间隔物。第二层多晶硅沉积在第一多晶硅层的上方并且在开口内的衬底上。图案化第二多晶硅层以形成栅电极和覆盖掩埋接触结的多晶硅接触，其中用于图案化的掩模不对准，并且覆盖掩埋接触结的间隔物的一部分被暴露，并且其中第二多晶硅层的一部分除了接触物以外，残留物残留。第二多晶硅层残留物被蚀刻掉，其中暴露的间隔物保护半导体衬底内的掩埋接触结点免受蚀刻，以在集成电路的制造中完成掩埋接触的形成。

39. 发明授权

US5652174A Unified stacked contact process for static random access memory (SRAM) having polysilicon load resistors 失效
标题翻译：具有多晶硅负载电阻的静态随机存取存储器（SRAM）的统一堆叠接触过程
公开(公告)号：US5652174A
公开(公告)日：1997-07-29
申请号：US650696
申请日：1996-05-20
申请人： Shou-Gwo Wuu , Mong-Song Liang , Chung-Hui Su , Chen-Jong Wang
发明人： Shou-Gwo Wuu , Mong-Song Liang , Chung-Hui Su , Chen-Jong Wang
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , H01L27/1112
摘要： A method is provide for a unified stacked contact structure which concurrently forms all the polysilicon interconnects and the polysilicon load resistors on a SRAM device. FETs formed from a first polysilicon layer are coated with a first insulating layer. A second polysilicon layer is deposited and patterned forming portions of the SRAM circuit and concurrently forming openings over FET source/drain areas. A second insulating layer is deposited, and contact openings are selectively etched in the insulating layer over the openings in the second polysilicon layer. The exposed second polysilicon layer in the contacts serve as an etch mask for etching the first insulating layer to the source/drain contact areas, thereby forming contacts self-aligned to the openings in the second polysilicon layer. The contact openings in the node contact areas also expose portions of the gate electrodes .of the SRAM driver transistors. The unified stacked contacts are completed by depositing and patterning a conformal third polysilicon layer that forms interconnections in the contact openings between the exposed patterned polysilicon layers, and the third polysilicon layer is also patterned to form the polysilicon load resistors. The number of masking and other process steps are substantially reduced.
摘要翻译：提供了一种统一的堆叠接触结构的方法，其同时形成SRAM器件上的所有多晶硅互连和多晶硅负载电阻。由第一多晶硅层形成的FET被涂覆有第一绝缘层。沉积第二多晶硅层并构图形成SRAM电路的部分，同时在FET源极/漏极区域上形成开口。沉积第二绝缘层，并且在第二多晶硅层中的开口上的绝缘层中选择性地蚀刻接触开口。触点中暴露的第二多晶硅层用作蚀刻掩模，用于将第一绝缘层蚀刻到源极/漏极接触区域，从而形成与第二多晶硅层中的开口自对准的触点。节点接触区域中的接触开口也暴露SRAM驱动晶体管的栅电极的部分。通过沉积和图案化形成在曝光的图案化多晶硅层之间的接触开口中形成互连的共形第三多晶硅层，并且第三多晶硅层也被图案化以形成多晶硅负载电阻来完成统一的堆叠接触。掩模和其他工艺步骤的数量显着减少。

40. 发明授权

US5610087A Method for fabricating narrow base width lateral bipolar junction transistor, on SOI layer 失效
标题翻译：在SOI层上制造窄基极宽度的双极结型晶体管的方法
公开(公告)号：US5610087A
公开(公告)日：1997-03-11
申请号：US565202
申请日：1995-11-09
申请人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
发明人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
IPC分类号： H01L21/331 , H01L21/84 , H01L29/73 , H01L21/265
CPC分类号： H01L29/66265 , H01L21/84 , H01L29/7317 , Y10S148/009
摘要： A process has been developed in which narrow base width, lateral bipolar junction transistors, and short channel length MOSFET devices, can be simultaneously fabricated, in a silicon on insulator layer. The narrow base width is defined by the width of an insulator sidewall spacer, formed on the sides of a polysilicon gate structure. The narrow base width, resulting in increased transistor gain and switching speed, along with reductions in parasitic capacitances, due to placing devices in a silicon on insulator layer, result in enhanced device performance.
摘要翻译：已经开发了一种可以在绝缘体上硅层中同时制造窄基极宽度，横向双极结晶体管和短沟道长度MOSFET器件的工艺。窄的基底宽度由形成在多晶硅栅极结构的侧面上的绝缘体侧壁间隔物的宽度限定。由于将器件放置在绝缘体上硅层中，导致晶体管增益和开关速度增加以及寄生电容降低的窄基极宽度导致器件性能的提高。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式