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1. 发明授权

US5728613A Method of using an insulator spacer to form a narrow base width lateral bipolar junction transistor 失效
标题翻译：使用绝缘体间隔物形成窄的基底宽度的横向双极结型晶体管的方法
公开(公告)号：US5728613A
公开(公告)日：1998-03-17
申请号：US622791
申请日：1996-03-27
申请人： Ching-Hsiang Hsu , Steve S. Chung , Shyh-Chyi Wong , Mong-Song Liang
发明人： Ching-Hsiang Hsu , Steve S. Chung , Shyh-Chyi Wong , Mong-Song Liang
IPC分类号： H01L21/331 , H01L21/8249 , H01L21/84 , H01L29/73 , H01L21/8238 , H01L21/8222
CPC分类号： H01L29/66265 , H01L21/8249 , H01L21/84 , H01L29/7317
摘要： A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, in a silicon on insulator layer. The narrow base width is defined by the width of an insulator sidewall spacer, formed on the sides of a polysilicon gate structure. The narrow base width, resulting in increased transistor gain and switching speed, along with reductions in parasitic capacitances, due to placing devices in a silicon on insulator layer, result in enhanced device performance.
摘要翻译：已经开发了一种在绝缘体上硅层中同时制造窄基极宽度，横向双极结晶体管和窄沟道长度MOSFET器件的工艺。窄的基底宽度由形成在多晶硅栅极结构的侧面上的绝缘体侧壁间隔物的宽度限定。由于将器件放置在绝缘体上硅层中，导致晶体管增益和开关速度增加以及寄生电容降低的窄基极宽度导致器件性能的提高。

2. 发明授权

US5818085A Body contact for a MOSFET device fabricated in an SOI layer 失效
标题翻译：用于在SOI层中制造的MOSFET器件的体接触
公开(公告)号：US5818085A
公开(公告)日：1998-10-06
申请号：US892337
申请日：1997-07-14
申请人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
发明人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
IPC分类号： H01L21/336 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L29/78612 , H01L29/78621
摘要： A MOSFET device structure, on a silicon on insulator layer, in which a body contact to the silicon on insulator layer exists, has been developed. The MOSFET device structure features a heavily doped P type body contact region in a lightly doped source and drain region of the MOSFET device structure, formed from an ion implantation through a metal silicide layer. The addition of the body contact results in more controllable device characteristics, in terms of drain currents, etc., than for counterparts fabricated in silicon on insulator layer, without the use of a body contact.
摘要翻译：已经开发了在绝缘体上硅层上存在与绝缘体上硅层接触体的MOSFET器件结构。 MOSFET器件结构在MOSFET器件结构的轻掺杂源极和漏极区域中具有重掺杂的P型体接触区域，其通过金属硅化物层的离子注入形成。身体接触的添加导致在漏极电流等方面比在绝缘体层上制造的对应物更不可控的器件特性，而不使用身体接触。

3. 发明授权

US5610087A Method for fabricating narrow base width lateral bipolar junction transistor, on SOI layer 失效
标题翻译：在SOI层上制造窄基极宽度的双极结型晶体管的方法
公开(公告)号：US5610087A
公开(公告)日：1997-03-11
申请号：US565202
申请日：1995-11-09
申请人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
发明人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
IPC分类号： H01L21/331 , H01L21/84 , H01L29/73 , H01L21/265
CPC分类号： H01L29/66265 , H01L21/84 , H01L29/7317 , Y10S148/009
摘要： A process has been developed in which narrow base width, lateral bipolar junction transistors, and short channel length MOSFET devices, can be simultaneously fabricated, in a silicon on insulator layer. The narrow base width is defined by the width of an insulator sidewall spacer, formed on the sides of a polysilicon gate structure. The narrow base width, resulting in increased transistor gain and switching speed, along with reductions in parasitic capacitances, due to placing devices in a silicon on insulator layer, result in enhanced device performance.
摘要翻译：已经开发了一种可以在绝缘体上硅层中同时制造窄基极宽度，横向双极结晶体管和短沟道长度MOSFET器件的工艺。窄的基底宽度由形成在多晶硅栅极结构的侧面上的绝缘体侧壁间隔物的宽度限定。由于将器件放置在绝缘体上硅层中，导致晶体管增益和开关速度增加以及寄生电容降低的窄基极宽度导致器件性能的提高。

4. 发明授权

US5705839A Gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology 失效
标题翻译：使用SOI技术控制横向双极结型晶体管的基极宽度的栅极间隔
公开(公告)号：US5705839A
公开(公告)日：1998-01-06
申请号：US857582
申请日：1997-05-16
申请人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
发明人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
IPC分类号： H01L21/331 , H01L21/8249 , H01L21/84 , H01L29/735 , H01L29/78 , H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/66265 , H01L21/8249 , H01L21/84 , H01L29/735 , H01L29/7833 , Y10S148/009 , Y10S148/096
摘要： A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, using a silicon on insulator approach. Insulator sidewall spacer and gate processing is used to produce narrow base widths for enhanced collector-base device characteristics, in terms of transistor gain, switching speeds and junction breakdowns.
摘要翻译：已经开发了一种使用绝缘体上硅法同时制造窄基极宽度，横向双极结晶体管和窄沟道长度MOSFET器件的工艺。在晶体管增益，开关速度和结击穿方面，使用绝缘体侧壁间隔件和栅极处理来产生窄的基极宽度，以增强集电极 - 基极器件特性。

5. 发明授权

US5567631A Method of forming gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology 失效
标题翻译：使用SOI技术形成栅极间隔物以控制横向双极结晶体管的基极宽度的方法
公开(公告)号：US5567631A
公开(公告)日：1996-10-22
申请号：US557654
申请日：1995-11-13
申请人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
发明人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
IPC分类号： H01L21/331 , H01L21/8249 , H01L21/84 , H01L29/735 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66265 , H01L21/8249 , H01L21/84 , H01L29/735 , H01L29/7833 , Y10S148/009 , Y10S148/096
摘要： A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, using a silicon on insulator approach. Insulator sidewall spacer and gate processing is used to produce narrow base widths for enhanced collector--base device characteristics, in terms of transistor gain, switching speeds and junction breakdowns.
摘要翻译：已经开发了一种使用绝缘体上硅法同时制造窄基极宽度，横向双极结晶体管和窄沟道长度MOSFET器件的工艺。在晶体管增益，开关速度和结击穿方面，使用绝缘体侧壁间隔件和栅极处理来产生窄的基极宽度，以增强集电极 - 基极器件特性。

6. 发明授权

US5573961A Method of making a body contact for a MOSFET device fabricated in an SOI layer 失效
标题翻译：制造在SOI层中的MOSFET器件接触体的方法
公开(公告)号：US5573961A
公开(公告)日：1996-11-12
申请号：US565201
申请日：1995-11-09
申请人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
发明人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
IPC分类号： H01L21/336 , H01L29/786 , H01L21/265
CPC分类号： H01L29/66772 , H01L29/78612 , H01L29/78621
摘要： A process for fabricating a MOSFET device, on a silicon on insulator layer, in which a body contact to the silicon on insulator layer exists, has been developed. The process features creating a heavily doped P type body contact region in a lightly doped source and drain region of the MOSFET, via ion implantation through a metal silicide layer. The addition of the body contact results in more controllable device characteristics, in terms of drain currents, etc., than for counterparts fabricated in silicon on insulator layer, without the use of a body contact.
摘要翻译：已经开发了在绝缘体上硅层上制造MOSFET器件的方法，其中存在与绝缘体上硅层接触的物体。该工艺特征是通过金属硅化物层的离子注入在MOSFET的轻掺杂源极和漏极区域中产生重掺杂的P型体接触区域。身体接触的添加导致在漏极电流等方面比在绝缘体层上制造的对应物更不可控的器件特性，而不使用身体接触。

7. 发明授权

US6124618A Dynamic threshold MOSFET using accumulated base BJT level shifter for low voltage sub-quarter micron transistor 有权
标题翻译：动态阈值MOSFET使用累积的基极BJT电平转换器用于低电压亚四分之一微米晶体管
公开(公告)号：US6124618A
公开(公告)日：2000-09-26
申请号：US379281
申请日：1999-08-23
申请人： Shyh-Chyi Wong , Mong-Song Liang
发明人： Shyh-Chyi Wong , Mong-Song Liang
IPC分类号： H01L27/06 , H01L27/12 , H01L29/72
CPC分类号： H01L27/0635 , H01L27/1203
摘要： A dynamic threshold voltage MOSFET to provide increase drain-to-source saturation current (I.sub.DSsat) and lower off current (I.sub.off) is described. The dynamic threshold voltage MOSFET has a first diffusion-well of a material of a first conductivity type formed at the surface of the substrate to form a bulk region. A source region and a drain region of a material of a second conductivity type are diffused into the diffusion-well. A first gate is then placed on a first oxide surface above the substrate between the source and drain regions. An accumulated base bipolar transistor is then placed on the semiconductor substrate. The base of the accumulated base bipolar transistor is connected to the gate, the emitter is connected to the diffusion-well. A resistor is connected between the emitter of the accumulated base bipolar transistor and a substrate biasing voltage source. A biasing circuit connected to the collector of the accumulated base bipolar transistor to provide a bias voltage for the accumulated base bipolar transistor.
摘要翻译：描述了提供增加漏极 - 源极饱和电流（IDSsat）和降低截止电流（Ioff）的动态阈值电压MOSFET。动态阈值电压MOSFET具有在衬底的表面形成的第一导电类型的材料的第一扩散阱，以形成体积区域。第二导电类型的材料的源极区域和漏极区域扩散到扩散井中。然后将第一栅极放置在源极和漏极区域之间的衬底上方的第一氧化物表面上。然后将积累的基极双极晶体管放置在半导体衬底上。累积的基极双极晶体管的基极连接到栅极，发射极连接到扩散井。一个电阻连接在累积的基极双极晶体管的发射极和一个衬底偏置电压源之间。连接到累积的基极双极晶体管的集电极的偏置电路，为累积的基极双极晶体管提供偏置电压。

8. 发明授权

US5644269A Cascode MOS current mirror with lateral bipolar junction transistor to enhance ouput signal swing 失效
标题翻译：串联MOS电流镜与横向双极结晶体管增强输出信号摆幅
公开(公告)号：US5644269A
公开(公告)日：1997-07-01
申请号：US570297
申请日：1995-12-11
申请人： Shyh-Chyi Wong , Mong-Song Liang
发明人： Shyh-Chyi Wong , Mong-Song Liang
IPC分类号： H03F1/22 , H03F3/345 , H03F3/45 , H03F3/16
CPC分类号： H03F1/223 , H03F3/345
摘要： A MOS transistor current mirror having a low output voltage is described. A first and second MOST's have their drains and gates connected respectively to form MOS diodes. The drain of the first MOST is connected to a control constant current source and the source of first MOST is connected to the drain of the second MOST. The drain and gate of the first MOST are connected to the base of a bipolar junction transistor (BJT). The collector of the BJT is connected to a first power supply line and the emitter is connected to the gate of a third MOST. A resistor is connected between the emitter of the BJT and the a second power supply line. The gate and drain of the second MOST is connected to the gate of a fourth MOST. The sources of the second and fourth MOST's are connected to the second power supply line. The drain of the fourth MOST is connected to the source of the third MOST. The drain of the third MOST is connected to external circuitry. The voltage developed between the drain of the third MOST and the second power supply line is relatively small to allow the voltage developed by the external circuitry to be relatively large, while said current mirror is providing a constant current to said external circuitry.
摘要翻译：描述具有低输出电压的MOS晶体管电流镜。第一和第二MOST的漏极和门分别连接形成MOS二极管。第一MOST的漏极连接到控制恒流源，第一MOST的源极连接到第二MOST的漏极。第一MOST的漏极和栅极连接到双极结型晶体管（BJT）的基极。 BJT的集电极连接到第一电源线，发射极连接到第三MOST的栅极。电阻器连接在BJT的发射极和第二电源线之间。第二MOST的栅极和漏极连接到第四MOST的栅极。第二和第四MOST的源极连接到第二电源线。第四MOST的漏极连接到第三MOST的源极。第三MOST的漏极连接到外部电路。在第三MOST的漏极和第二电源线之间产生的电压相对较小，以允许由外部电路产生的电压相对较大，而所述电流镜向所述外部电路提供恒定的电流。

9. 发明授权

US06181542B2 Method of making a stack-polysilicon capacitor-coupled dual power supply input/output protection circuit 有权
标题翻译：制造堆叠多晶硅电容耦合双电源输入/输出保护电路的方法
公开(公告)号：US06181542B2
公开(公告)日：2001-01-30
申请号：US09216824
申请日：1998-12-21
申请人： Mong-Song Liang , Shyh-Chyi Wong
发明人： Mong-Song Liang , Shyh-Chyi Wong
IPC分类号： H02H300
CPC分类号： H03K19/00315 , H01L27/0251 , H01L27/0266
摘要： An interface buffer circuit connected at an interface of circuits having a high voltage power supply and circuits having a low voltage power supply, prevents damage due to application of the high voltage power supply to the output terminal of the interface buffer circuit. The interface buffer circuit has a predriver circuit and an interface buffer circuit. The interface buffer circuit has an interface buffer protection circuit. The interface buffer protection circuit consists of an inverter circuit. The inverter circuit has an input connected to the input of the interface driver circuit and an output connected to the gate of a MOS transistor. The source of the MOS transistor is connected to the predriver circuit to control the output of the predriver circuit. The interface buffer protection circuit further has a coupling capacitor connected to interface driver circuit. When a voltage level at the output of the interface driver circuit approaches that of the high voltage power supply, a voltage level input of the inverter causes the output of the inverter circuit to assume a voltage level that will turn off the MOS transistor capturing the voltage level at the input of the interface driver circuit to prevent damage.
摘要翻译：连接在具有高电压电源的电路和具有低电压电源的电路的接口处的接口缓冲电路防止由于向接口缓冲电路的输出端施加高电压电源而造成的损坏。接口缓冲电路具有预驱动电路和接口缓冲电路。接口缓冲电路具有接口缓冲保护电路。接口缓冲保护电路由逆变电路组成。逆变器电路具有连接到接口驱动电路的输入的输入端和与MOS晶体管的栅极连接的输出。 MOS晶体管的源极连接到预驱动电路以控制预驱动电路的输出。接口缓冲保护电路还具有连接到接口驱动电路的耦合电容。当接口驱动电路的输出端的电压电平接近高电压电源的电压时，反相器的电压电平输入使逆变器电路的输出呈现一个电压电平，该电压将关闭MOS晶体管，捕获电压电平在接口驱动电路的输入端以防止损坏。

10. 发明授权

US6051458A Drain and source engineering for ESD-protection transistors 失效
标题翻译： ESD保护晶体管的漏极和源极工程
公开(公告)号：US6051458A
公开(公告)日：2000-04-18
申请号：US72254
申请日：1998-05-04
申请人： Mong-Song Liang , Shyh-Chyi Wong
发明人： Mong-Song Liang , Shyh-Chyi Wong
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/0922 , H01L21/823814 , Y10S438/919
摘要： A semiconductor device is formed on a semiconductor substrate with an N-well and a P-well with source/drain sites in the N-well and in the P-well by the following steps. Form a gate oxide layer and a gate electrode layer patterned into a gate electrode stack with sidewalls over a substrate with N-well and P-well. Form N- LDS/LDD regions in the P-well. Form N- LDS/LDD regions in the P-well and P- lightly doped halo regions in the P-well below the source site and the drain site in the P-well. Form a counter doped halo region doped with N type dopant below the source region site in the P-well. Form spacers on the gate electrode sidewalls. Then, form lightly doped regions self-aligned with the gate electrode in the source/drain sites. Form N+ type doped source/drain regions deeper than the N- LDS/LDD regions in the P-well in the source/drain sites. Form P+ type doped source/drain regions deeper than the P- LDS/LDD regions in the N-well in the source/drain sites.
摘要翻译：半导体器件通过以下步骤在N阱和P阱中的N阱和P阱形成在半导体衬底上，源极/漏极位置在N阱中。形成栅极氧化物层和栅极电极层，其图案化成具有N阱和P阱的衬底上的侧壁的栅电极堆叠。在P井中形成N- LDS / LDD区域。在P阱下面的P阱中的P-阱和P-轻掺杂的晕区中的N-LDS / LDD区域形成在P阱中的漏极位置。在P阱的源极区域的下方形成掺杂有N型掺杂剂的反掺杂晕圈。在栅电极侧壁上形成间隔物。然后，形成与源/漏部位中的栅电极自对准的轻掺杂区域。形式N +型掺杂的源极/漏极区域比源极/漏极区域的P阱中的N-LDS / LDD区域更深。形成P +型掺杂的源极/漏极区，比源极/漏极位置的N阱中的P- LDS / LDD区更深。

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