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31. 发明申请

US20050141299A1 Semiconductor memory device for controlling cell block with state machine 失效
标题翻译：用状态机控制电池块的半导体存储器件
公开(公告)号：US20050141299A1
公开(公告)日：2005-06-30
申请号：US11015475
申请日：2004-12-20
申请人： Sang-Hoon Hong , Jae-Bum Ko , Se-Jun Kim
发明人： Sang-Hoon Hong , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G11C7/10 , G11C7/22 , G11C8/12 , G11C29/00
CPC分类号： G11C7/22 , G11C8/12
摘要： A semiconductor memory device for an effective data access operation includes a cell area having N+1 number of unit cell blocks, each including M number of word lines, for storing a data in a unit cell corresponding to an inputted address; N+1 number of unit controlling blocks having respective state machines and corresponding to the respective N+1 unit cell blocks for controlling a data restoration that is accessed from a first unit cell block selected from the N+1 unit cell blocks into the first unit cell block or a second unit cell block; and a driving controlling block for controlling the N+1 unit cell blocks so that the N+1 unit controlling means are in one of first to fourth operation states.
摘要翻译：一种用于有效数据存取操作的半导体存储器件包括：具有N + 1个单位单元块数量的单元区域，每个单元单元块包括M个字线，用于存储与输入地址对应的单位单元中的数据; N + 1个单元控制块，具有各自的状态机，并且对应于用于控制从从N + 1个单元块选择的第一单元单元块访问到第一单元的数据恢复的相应N + 1个单位单元块单元块或第二单元单元块; 以及驱动控制块，用于控制N + 1个单元块，使得N + 1单元控制装置处于第一至第四操作状态之一。

32. 发明授权

US06859081B2 Duty cycle correction circuit and delay locked loop having the same 失效
标题翻译：占空比校正电路和延迟锁定环具有相同的作用
公开(公告)号：US06859081B2
公开(公告)日：2005-02-22
申请号：US10638994
申请日：2003-08-11
申请人： Sang-Hoon Hong , Se-Jun Kim , Jeong-Hoon Kook
发明人： Sang-Hoon Hong , Se-Jun Kim , Jeong-Hoon Kook
IPC分类号： H03L7/08 , H03K5/156 , H03L7/081 , H03L7/089 , H03K3/017
CPC分类号： H03L7/0805 , H03K5/1565 , H03L7/0812 , H03L7/0891
摘要： A duty cycle correction (DCC) circuit including first and second clock dividers for dividing ordinary and sub-input clocks. Optional first and second variable delay devices delay the divided clocks. First and second mixers mix an optionally delayed ordinary divided clock and sub-ordinary divided clock, or an ordinary divided clock and an optionally delayed sub-ordinary divided clock. A logic combination device is included to produce a clock at the same frequency as the ordinary and sub-input clocks, with a corrected duty cycle.
摘要翻译：一种占空比校正（DCC）电路，包括用于分割普通和子输入时钟的第一和第二时钟分频器。可选的第一和第二可变延迟器件延迟分频时钟。第一和第二混频器混合可选地延迟的普通分频时钟和次普通分频时钟，或普通分频时钟和可选延迟的次普通分频时钟。包括逻辑组合装置以产生与正常和子输入时钟相同频率的时钟，具有校正的占空比。

33. 发明授权

US06813196B2 High speed interface type semiconductor memory device 失效
标题翻译：高速接口型半导体存储器件
公开(公告)号：US06813196B2
公开(公告)日：2004-11-02
申请号：US09892549
申请日：2001-06-28
申请人： Yong Jae Park , Se Jun Kim
发明人： Yong Jae Park , Se Jun Kim
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： The present invention discloses a high speed interface type semiconductor memory device which can transmit data of a plurality of DRAMs of a module to a controller by using only one data strobe clock signal. The high speed interface type semiconductor memory device includes a DRAM module unit for generating a strobe clock signal for synchronizing a data signal in a read operation in a DRAM farthest from a controller among a plurality of DRAMs, providing the strobe clock signal to the other DRAMs, and transmitting data to the controller in the read operation, and a controller for transmitting a clock signal and data signals synchronized with the clock signal to the plurality of DRAMs, and receiving data signals from the DRAMs.
摘要翻译：本发明公开了一种高速接口型半导体存储器件，其可以通过仅使用一个数据选通时钟信号将模块的多个DRAM的数据传输到控制器。高速接口型半导体存储器件包括：DRAM模块单元，用于产生用于在多个DRAM中与控制器最远的DRAM中的读取操作中的数据信号同步的选通时钟信号，将选通时钟信号提供给其它DRAM ，以及在读取操作中向控制器发送数据，以及用于将时钟信号和与时钟信号同步的数据信号发送到多个DRAM的控制器，以及从DRAM接收数据信号。

34. 发明授权

US06686788B2 Delay circuit of clock synchronization device using delay cells having wide delay range 失效
标题翻译：使用具有宽延迟范围的延迟单元的时钟同步装置的延迟电路
公开(公告)号：US06686788B2
公开(公告)日：2004-02-03
申请号：US10140280
申请日：2002-05-06
申请人： Se Jun Kim , Sang Hoon Hong
发明人： Se Jun Kim , Sang Hoon Hong
IPC分类号： H03H1126
CPC分类号： H03K5/133 , H03K2005/00026 , H03K2005/00208 , H03K2005/00234 , H03L7/0812 , H03L7/0995
摘要： A delay circuit of a clock synchronization device that includes an operational amplifier for setting the level of a current control voltage according to a voltage difference between a regulation voltage and a reference voltage. A number of unit delay cells connected in series are included, each having a delay time set according to a resistance control voltage and the current control voltage. Also, a variable resistance unit is included having a resistance value adjusted according to the resistance control voltage, where the variable resistance unit includes a cross coupled adjustment device that outputs signals to a next unit delay cell. The delay cells are controlled by using the operational amplifier and a replica cell to have a wide delay range. As a result, the working range can be set wide, jitters may be reduced and the chip size may also be reduced.
摘要翻译：时钟同步装置的延迟电路，其包括用于根据调节电压和参考电压之间的电压差来设定电流控制电压的电平的运算放大器。包括串联连接的多个单元延迟单元，每个具有根据电阻控制电压和电流控制电压设置的延迟时间。此外，包括根据电阻控制电压调整的电阻值的可变电阻单元，其中可变电阻单元包括向下一个单位延迟单元输出信号的交叉耦合调整装置。通过使用运算放大器和复制单元来控制延迟单元具有宽的延迟范围。结果，可以将工作范围设定得很宽，可能减少抖动，并且芯片尺寸也可能降低。

35. 发明授权

US06597298B2 Clock synchronization device 失效
公开(公告)号：US06597298B2
公开(公告)日：2003-07-22
申请号：US10180131
申请日：2002-06-27
申请人： Se Jun Kim , Sang Hoon Hong
发明人： Se Jun Kim , Sang Hoon Hong
IPC分类号： H03M148
CPC分类号： H03L7/089 , H03L7/0812 , H04L7/0037
摘要： A clock synchronization device divides a digital-to-analog converting unit into main and sub digital-to-analog converters and operates both main and sub digital-to-analog converting units if an output voltage of the digital-to-analog converting unit is lower than a reference voltage based on a voltage obtained when the delay rate of a variable delay line VDL is sharply increased or operates only the main digital-to-analog converting unit if the output voltage of the digital-to-analog converting unit is higher than the reference voltage. As a result, the clock synchronization device can make the output voltage of the digital-to-analog converting unit be linear with respect to a digital code, thereby improving a jitter property in a band with a very large gain of the variable delay line.

36. 发明授权

US06552587B2 Synchronous semiconductor device for adjusting phase offset in a delay locked loop 有权
公开(公告)号：US06552587B2
公开(公告)日：2003-04-22
申请号：US10033004
申请日：2001-12-28
申请人： Se-Jun Kim , Jae-Kyung Wee , Yong-Jae Park
发明人： Se-Jun Kim , Jae-Kyung Wee , Yong-Jae Park
IPC分类号： H03L706
CPC分类号： G11C29/50012 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C29/50 , H03L7/0814 , H03L7/0891
摘要： A synchronous semiconductor device having a delay locked loop capable of adjusting phase offset between an external clock signal and an internal clock signal after a packaging process is completed is disclosed. The disclosed synchronous semiconductor device may include a replica delay for replicating delay time of an internal circuit and a delay controller for controlling the replicated delay time.

37. 发明申请

US20110204430A1 NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20110204430A1
公开(公告)日：2011-08-25
申请号：US13097479
申请日：2011-04-29
申请人： Se Jun KIM , Eun Seok CHOI , Kyoung Hwan PARK , Hyun Seung YOO , Myung Shik LEE , Young Ok HONG , Jung Ryul AHN , Yong Top KIM , Kyung Pil HWANG , Won Sic WOO , Jae Young PARK , Ki Hong LEE , Ki Seon PARK , Moon Sig JOO
发明人： Se Jun KIM , Eun Seok CHOI , Kyoung Hwan PARK , Hyun Seung YOO , Myung Shik LEE , Young Ok HONG , Jung Ryul AHN , Yong Top KIM , Kyung Pil HWANG , Won Sic WOO , Jae Young PARK , Ki Hong LEE , Ki Seon PARK , Moon Sig JOO
IPC分类号： H01L29/792 , B82Y99/00
CPC分类号： H01L29/513 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/792
摘要： A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
摘要翻译：提供了一种非易失性存储器件及其制造方法，以防止存储在电荷陷阱层中的电荷移动到相邻存储器单元。制造非易失性存储器件的方法包括在半导体衬底上形成第一电介质层，其中有源区由隔离层限定，在第一电介质层上形成电荷陷阱层，去除第一介电层和电荷陷阱层在隔离层上，在包括电荷陷阱层的隔离层上形成第二电介质层，并在第二介电层上形成导电层。

38. 发明授权

US07955960B2 Nonvolatile memory device and method of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07955960B2
公开(公告)日：2011-06-07
申请号：US12052914
申请日：2008-03-21
申请人： Se Jun Kim , Eun Seok Choi , Kyoung Hwan Park , Hyun Seung Yoo , Myung Shik Lee , Young Ok Hong , Jung Ryul Ahn , Yong Top Kim , Kyung Pil Hwang , Won Sic Woo , Jae Young Park , Ki Hong Lee , Ki Seon Park , Moon Sig Joo
发明人： Se Jun Kim , Eun Seok Choi , Kyoung Hwan Park , Hyun Seung Yoo , Myung Shik Lee , Young Ok Hong , Jung Ryul Ahn , Yong Top Kim , Kyung Pil Hwang , Won Sic Woo , Jae Young Park , Ki Hong Lee , Ki Seon Park , Moon Sig Joo
IPC分类号： H01L21/336
CPC分类号： H01L29/513 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/792
摘要： A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
摘要翻译：提供了一种非易失性存储器件及其制造方法，以防止存储在电荷陷阱层中的电荷移动到相邻存储器单元。制造非易失性存储器件的方法包括在半导体衬底上形成第一电介质层，其中有源区由隔离层限定，在第一电介质层上形成电荷陷阱层，去除第一介电层和电荷陷阱层在隔离层上，在包括电荷陷阱层的隔离层上形成第二电介质层，并在第二介电层上形成导电层。

39. 发明申请

US20080042737A1 Band-gap reference voltage generator 失效
标题翻译：带隙基准电压发生器
公开(公告)号：US20080042737A1
公开(公告)日：2008-02-21
申请号：US11648462
申请日：2006-12-28
申请人： Se Jun Kim , Chun Seok Jeong
发明人： Se Jun Kim , Chun Seok Jeong
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A band-gap reference voltage generator includes a first reference current generator, a second reference current generator, and a reference voltage generator. The first reference current generator includes: a driver generating a first reference current in response to a first voltage signal generated by comparison of the unique voltage and the thermal voltage. The second reference current generator includes a driver generating a second reference current in response to a second voltage signal generated by comparison of a division voltage of a power-supply voltage and the unique voltage. The reference voltage generator includes a driver forming current mirrors in association with each of the first reference current generator and the second reference current generator, respectively, and generating a third reference current and a fourth reference current via the formed current mirrors, and a current-voltage converter converting the sum of the third reference current and the fourth reference current into a reference voltage, and outputting the reference voltage.
摘要翻译：带隙参考电压发生器包括第一参考电流发生器，第二参考电流发生器和参考电压发生器。第一参考电流发生器包括：响应于通过比较唯一电压和热电压而产生的第一电压信号而产生第一参考电流的驱动器。第二参考电流发生器包括响应于通过比较电源电压的分压和独特电压而产生的第二电压信号而产生第二参考电流的驱动器。参考电压发生器包括分别与第一参考电流发生器和第二参考电流发生器相关联地形成电流镜的驱动器，并且经由形成的电流镜产生第三参考电流和第四参考电流，电压转换器将第三参考电流和第四参考电流的和转换成参考电压，并输出参考电压。

40. 发明授权

US07174418B2 Semiconductor memory device for enhancing refresh operation in high speed data access 有权
标题翻译：用于增强高速数据访问中的刷新操作的半导体存储器件
公开(公告)号：US07174418B2
公开(公告)日：2007-02-06
申请号：US10749766
申请日：2003-12-30
申请人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
发明人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G06F12/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40618
摘要： A semiconductor device for refreshing data stored in a memory device includes a cell area having N+1 number of unit cell blocks, each including M number of word lines which respectively are coupled to a plurality of unit cells; a tag block having N+1 number of unit tag blocks, each storing at least one physical cell block address denoting a row address storing a data; and a control block for controlling the tag block and the predetermined cell block table for refreshing the data in the plurality of unit cells coupled to a word line in response to the physical cell block address.
摘要翻译：用于刷新存储在存储器件中的数据的半导体器件包括具有N + 1个单元单元块的单元区域，每个单元单元块包括分别耦合到多个单位单元的M个字线; 具有N + 1个单位标签块的标签块，每个存储表示存储数据的行地址的至少一个物理单元块地址; 以及控制块，用于控制标签块和预定的单元块表，用于响应于物理单元块地址刷新与字线耦合的多个单元单元中的数据。

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