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31. 发明授权

US08207570B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US08207570B2
公开(公告)日：2012-06-26
申请号：US12851896
申请日：2010-08-06
申请人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu
发明人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu
IPC分类号： H01L29/788
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/31144 , H01L27/11526 , H01L27/11543
摘要： Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.
摘要翻译：一些实施方案包括沿着牺牲材料形成聚合物间隔物，去除牺牲材料，以及在制造集成电路期间利用聚合物间隔物作为掩模。聚合物间隔物掩模可以例如用于对闪存阵列的闪光栅图案进行图案化。在一些实施方案中，聚合物同时形成跨越大的牺牲结构和小的牺牲结构。聚合物在大的牺牲结构上比通过小的牺牲结构更厚，并且这种厚度的差异被用于利用单个光掩模制造高密度结构和低密度结构。

32. 发明申请

US20110008970A1 Methods of Forming Semiconductor Constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20110008970A1
公开(公告)日：2011-01-13
申请号：US12886459
申请日：2010-09-20
申请人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu , Luan C. Tran
发明人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu , Luan C. Tran
IPC分类号： H01L21/31
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/76232 , H01L27/105 , H01L27/1052
摘要： The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.
摘要翻译：本发明包括形成用于半导体结构的隔离区域的方法。可以在半导体衬底上形成并图案化硬掩模，其中图案化的硬掩模暴露衬底的区域。可以蚀刻这样的暴露区域以形成具有第一宽度的第一开口。第一个开口用含碳材料的共形层变窄。穿过保形层以沿着狭窄的开口的底部露出衬底。去除暴露的衬底以形成连接到第一开口的第二开口，并且具有小于第一宽度的第二宽度。然后从第一开口内去除含碳材料，并且电绝缘材料形成在第一和第二开口内。电绝缘材料可以基本上填充第一开口，并在第二开口内留下空隙。

33. 发明申请

US20100216307A1 SIMPLIFIED PITCH DOUBLING PROCESS FLOW 有权
标题翻译：简化的PITCH DOUBLING PROCESS FLOW
公开(公告)号：US20100216307A1
公开(公告)日：2010-08-26
申请号：US12771951
申请日：2010-04-30
申请人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
发明人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
IPC分类号： H01L21/306 , H01L21/314
CPC分类号： H01L27/04 , H01L21/0338 , H01L21/3088 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
摘要翻译：一种用于制造半导体器件的方法包括对一层光致抗蚀剂材料进行构图以形成多个心轴。该方法还包括通过原子层沉积（ALD）工艺在多个心轴上沉积氧化物材料。该方法还包括从暴露的水平表面各向异性地蚀刻氧化物材料。该方法还包括选择性地蚀刻光刻胶材料。

34. 发明申请

US20100210111A1 PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES 有权
标题翻译：相对于光刻特征的PITCH减少图案
公开(公告)号：US20100210111A1
公开(公告)日：2010-08-19
申请号：US12769071
申请日：2010-04-28
申请人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi (Jenny) Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
发明人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi (Jenny) Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L21/308
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.
摘要翻译：通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。间距乘法用于形成第一模式的相对较小的特征。通过图案化无定形碳层来实现间距倍增。然后在非晶碳侧壁上形成侧壁间隔物，然后将其去除; 侧壁间隔物限定第一掩模图案。然后沉积底部抗反射涂层（BARC）以形成平坦表面，并且在BARC上形成光致抗蚀剂层。接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，其转移到BARC。将组合图案转移到下面的非晶硅层。然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。然后将组合的掩模图案蚀刻到下面的基底中。

35. 发明授权

US07718540B2 Pitch reduced patterns relative to photolithography features 有权
标题翻译：相对于光刻特征的间距减小
公开(公告)号：US07718540B2
公开(公告)日：2010-05-18
申请号：US11670296
申请日：2007-02-01
申请人： Luan Tran , William T Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K Abatchev , Gurtej S Sandhu , D. Mark Durcan
发明人： Luan Tran , William T Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K Abatchev , Gurtej S Sandhu , D. Mark Durcan
IPC分类号： H01L21/302
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.
摘要翻译：通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。然后在无定形碳的侧壁上形成侧壁间隔物。去除无定形碳，留下限定第一掩模图案的侧壁间隔物。然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

36. 发明申请

US20100092891A1 PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES 有权
标题翻译：相对于光刻特征的PITCH减少图案
公开(公告)号：US20100092891A1
公开(公告)日：2010-04-15
申请号：US12636581
申请日：2009-12-11
申请人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
发明人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： G03F7/20
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.
摘要翻译：通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。然后在无定形碳的侧壁上形成侧壁间隔物。去除无定形碳，留下限定第一掩模图案的侧壁间隔物。然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

37. 发明申请

US20100062580A1 Fabrication processes for forming dual depth trenches using a dry etch that deposits a polymer 有权
标题翻译：使用沉积聚合物的干蚀刻形成双深度沟槽的制造工艺
公开(公告)号：US20100062580A1
公开(公告)日：2010-03-11
申请号：US12396952
申请日：2009-03-03
申请人： Xiaolong Fang , Ramakanth Alapati , Tuman E. Allen
发明人： Xiaolong Fang , Ramakanth Alapati , Tuman E. Allen
IPC分类号： H01L21/762 , H01L21/3065
CPC分类号： H01L27/115 , H01L21/76229 , H01L27/1052 , H01L27/11526 , H01L27/11543
摘要： Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes that utilize disclosed dry etching processes to form a significant depth Δ between an array trench depth and a periphery trench depth. One etching method creates a trench delta depth utilizing a single dry etch step, while two other etching methods create a trench Δ depth by utilizing three dry etch steps.
摘要翻译：描述了用于制造半导体器件的沟槽隔离结构和形成方法。使用若干处理方案形成沟槽隔离结构，这些处理方案利用公开的干蚀刻工艺以形成显着的深度＆Dgr; 在阵列沟槽深度和外围沟槽深度之间。一种蚀刻方法利用单次干蚀刻步骤产生沟槽三角形深度，而另外两种蚀刻方法产生沟槽＆Dgr; 利用三个干蚀刻步骤进行深度测量。

38. 发明申请

US20080220600A1 Semiconductor constructions, methods of forming multiple lines, and methods of forming high density structures and low density structures with a single photomask 有权
标题翻译：半导体结构，形成多条线的方法，以及用单个光掩模形成高密度结构和低密度结构的方法
公开(公告)号：US20080220600A1
公开(公告)日：2008-09-11
申请号：US11714378
申请日：2007-03-05
申请人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu
发明人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu
IPC分类号： H01L21/20
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/31144 , H01L27/11526 , H01L27/11543
摘要： Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.
摘要翻译：一些实施方案包括沿着牺牲材料形成聚合物间隔物，去除牺牲材料，以及在制造集成电路期间利用聚合物间隔物作为掩模。聚合物间隔物掩模可以例如用于对闪存阵列的闪光栅图案进行图案化。在一些实施方案中，聚合物同时形成跨越大的牺牲结构和小的牺牲结构。聚合物在大的牺牲结构上比通过小的牺牲结构更厚，并且这种厚度的差异被用于利用单个光掩模制造高密度结构和低密度结构。

39. 发明申请

US20140051233A1 METHODS OF THINNING AND/OR DICING SEMICONDUCTING SUBSTRATES HAVING INTEGRATED CIRCUIT PRODUCTS FORMED THEREON 有权
标题翻译：具有形成集成电路产品的薄膜和/或二极管半导体衬底的方法
公开(公告)号：US20140051233A1
公开(公告)日：2014-02-20
申请号：US13585974
申请日：2012-08-15
申请人： Rahul Agarwal , Ramakanth Alapati , Jon Greenwood
发明人： Rahul Agarwal , Ramakanth Alapati , Jon Greenwood
IPC分类号： H01L21/78 , H01L21/304
CPC分类号： H01L21/78 , H01L21/6836 , H01L2221/68327 , H01L2221/6834
摘要： One illustrative method disclosed herein includes forming a plurality of die above a crystalline semiconducting substrate, irradiating and cooling an edge region of the substrate to form an amorphous region in the edge region of the substrate and, after forming the amorphous region, performing at least one process operation to reduce the thickness of the substrate.
摘要翻译：本文公开的一种说明性方法包括在晶体半导体衬底上形成多个管芯，照射和冷却衬底的边缘区域以在衬底的边缘区域中形成非晶区域，并且在形成非晶区域之后，执行至少一个工艺操作以减小基板的厚度。

40. 发明申请

US20120238077A1 Methods of Forming High Density Structures and Low Density Structures with a Single Photomask 有权
标题翻译：用单一光掩模形成高密度结构和低密度结构的方法
公开(公告)号：US20120238077A1
公开(公告)日：2012-09-20
申请号：US13485869
申请日：2012-05-31
申请人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu
发明人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu
IPC分类号： H01L21/302 , H01L21/20
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/31144 , H01L27/11526 , H01L27/11543
摘要： Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.
摘要翻译：一些实施方案包括沿着牺牲材料形成聚合物间隔物，去除牺牲材料，以及在制造集成电路期间利用聚合物间隔物作为掩模。聚合物间隔物掩模可以例如用于对闪存阵列的闪光栅图案进行图案化。在一些实施方案中，聚合物同时形成跨越大的牺牲结构和小的牺牲结构。聚合物在大的牺牲结构上比通过小的牺牲结构更厚，并且这种厚度的差异被用于利用单个光掩模制造高密度结构和低密度结构。

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