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31. 发明申请

US20080191307A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080191307A1
公开(公告)日：2008-08-14
申请号：US11971096
申请日：2008-01-08
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/861
CPC分类号： H01L29/7802 , H01L21/02164 , H01L21/0217 , H01L21/02321 , H01L21/2003 , H01L21/265 , H01L21/2658 , H01L21/26586 , H01L21/28008 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/823885 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4236 , H01L29/42368 , H01L29/66537 , H01L29/66666 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/7835
摘要： A semiconductor structure includes a number of semiconductor regions, a pair of dielectric regions and a pair of terminals. The first and second regions of the structure are respectively coupled to the first and second terminals. The third region of the structure is disposed between the first and second regions. The dielectric regions extend into the third region. A concentration of doping impurities present in the third region and a distance between the dielectric regions define an electrical characteristic of the structure. The electrical characteristic of the structure is independent of the width of the dielectric regions width. The first and second regions are of opposite conductivity types. The structure optionally includes a fourth region that extends into the third region, and surrounds a portion of the pair of dielectric regions. The interface region between the dielectric regions and the fourth region includes intentionally introduced charges.
摘要翻译：半导体结构包括多个半导体区域，一对电介质区域和一对端子。该结构的第一和第二区域分别耦合到第一和第二端子。结构的第三区域设置在第一和第二区域之间。电介质区域延伸到第三区域。存在于第三区域中的掺杂杂质的浓度和电介质区域之间的距离限定了该结构的电特性。该结构的电气特性与电介质区域的宽度无关。第一和第二区域具有相反的导电类型。该结构可选地包括延伸到第三区域中并围绕该对电介质区域的一部分的第四区域。电介质区域和第四区域之间的界面区域包括有意引入的电荷。

32. 发明申请

US20080164516A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080164516A1
公开(公告)日：2008-07-10
申请号：US11971123
申请日：2008-01-08
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L21/02164 , H01L21/0217 , H01L21/02321 , H01L21/2003 , H01L21/265 , H01L21/2658 , H01L21/26586 , H01L21/28008 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/823885 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4236 , H01L29/42368 , H01L29/66537 , H01L29/66666 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/7835
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type. Each of the pair of trenches consists essentially of a dielectric material disposed therein and a concentration of doping impurities present in the semiconductor layer of the second conductivity type and a distance between the pair of trenches define an electrical characteristic of the semiconductor device. The semiconductor device further includes a control gate coupled to the semiconductor layer of the second conductivity type and a source region coupled to the semiconductor layer of the second conductivity type.
摘要翻译：半导体器件包括形成在其上的第一导电类型的半导体层和第二导电类型的半导体层。半导体器件还包括延伸第二预定距离的第二预定距离的第二预定距离的第二导电类型的半导体层的主体层和延伸到第二导电类型的半导体层的一对沟槽。一对沟槽中的每一个基本上由设置在其中的介电材料组成，并且存在于第二导电类型的半导体层中的掺杂杂质的浓度和该对沟槽之间的距离限定了半导体器件的电特性。半导体器件还包括耦合到第二导电类型的半导体层的控制栅极和耦合到第二导电类型的半导体层的源极区域。

33. 发明授权

US07326995B2 Trench MIS device having implanted drain-drift region and thick bottom oxide 有权
标题翻译：沟槽MIS器件具有植入漏极漂移区域和厚底部氧化物
公开(公告)号：US07326995B2
公开(公告)日：2008-02-05
申请号：US11158382
申请日：2005-06-22
申请人： Mohamed N. Darwish , King Owyang
发明人： Mohamed N. Darwish , King Owyang
IPC分类号： H01L29/72
CPC分类号： H01L29/7813 , H01L21/2253 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/823487 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/42368
摘要： A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. Therefore, in embodiments where the thermal budget of the process is limited following the implant of the drain-drift region, the PN junctions between the drain-drift region and the epitaxial layer are self-aligned with the edges of the thick bottom oxide. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The relatively flat dopant profile in the channel region provides an increased punchthrough voltage and low threshold voltage.
摘要翻译：沟槽MIS器件形成在覆盖在N +衬底上的P外延层中。在一个实施例中，器件包括在沟槽底部的厚氧化物层和从沟槽的底部延伸到衬底的N型漏 - 漂移区。厚的绝缘层减小了栅极和漏极之间的电容，从而提高了器件在高频下工作的能力。优选地，漏极漂移区域至少部分地通过在沟槽的侧壁上制造间隔物并且在侧壁间隔物之间并通过沟槽的底部注入N型掺杂剂而形成。厚的底部氧化物层形成在沟槽的底部，同时侧壁间隔物仍然在位。因此，在漏极 - 漂移区的注入之后，工艺的热预算受到限制的实施例中，漏 - 漂移区和外延层之间的PN结与厚的底部氧化物的边缘自对准。漏极漂移区可以比在N外延层中形成的常规“漂移区”更重的掺杂。因此，器件具有低导通电阻。通道区域中相对平坦的掺杂物分布提供了增加的穿通电压和低阈值电压。

34. 发明授权

US07009247B2 Trench MIS device with thick oxide layer in bottom of gate contact trench 有权
公开(公告)号：US07009247B2
公开(公告)日：2006-03-07
申请号：US10722984
申请日：2003-11-25
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L21/2253 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/28238 , H01L21/823487 , H01L29/0634 , H01L29/0847 , H01L29/1095 , H01L29/42368 , H01L29/4983 , H01L29/512 , H01L29/518 , H01L29/66621 , H01L29/7834
摘要： A trench MIS device includes a thick dielectric layer at the bottom of the trench. The thick dielectric layer can be formed by the deposition or thermal growth of a dielectric material, such as silicon dioxide, on the bottom portion of the trench. The thick dielectric layer, which reduces the capacitance between the drain and gate of the device, can be formed in both the active areas of the device, where the switching function is performed, and in the inactive areas where, among other things, contacts are made to the gate electrode.

35. 发明授权

US06764906B2 Method for making trench mosfet having implanted drain-drift region 有权
标题翻译：制造具有注入漏极漂移区域的沟槽MOSFET的方法
公开(公告)号：US06764906B2
公开(公告)日：2004-07-20
申请号：US10317568
申请日：2002-12-12
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H02L21336
CPC分类号： H01L29/7813 , H01L21/2253 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. A trench is formed in the epitaxial layer. A deep implanted N layer is formed below the trench at the interface between the substrate and the epitaxial layer, and N-type dopant is implant through the bottom of the trench to form an N region in the epitaxial layer below the trench but above and separated from the deep N layer. The structure is heated to cause the N layer to diffuse upward and the N region to diffuse downward. The diffusions merge to form a continuous N-type drain-drift region extending from the bottom of the trench to the substrate. Alternatively, the drain-drift region may be formed by implanting N-type dopant through the bottom of the trench at different energies, creating a stack of N-type regions that extend from the bottom of the trench to the substrate.
摘要翻译：在包括覆盖在N +衬底上的P型外延层的结构中形成沟槽MOSFET。在外延层中形成沟槽。在衬底和外延层之间的界面处在沟槽下方形成深深注入的N层，并且N型掺杂剂通过沟槽的底部注入，以在沟槽下方的外延层中形成N区，但在上方并分离从深N层。加热结构使N层向上扩散，N区向下扩散。扩散合并形成从沟槽的底部延伸到衬底的连续的N型漏 - 漂移区。或者，可以通过在不同能量下通过沟槽的底部注入N型掺杂剂形成漏极 - 漂移区域，从而形成从沟槽的底部延伸到衬底的N型区域堆叠。

36. 发明授权

US06603188B1 Polysilicon-edge, low-power, high-frequency bipolar transistor and method of forming the transistor 有权
公开(公告)号：US06603188B1
公开(公告)日：2003-08-05
申请号：US10207628
申请日：2002-07-29
申请人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
发明人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
IPC分类号： H01L27082
CPC分类号： H01L29/66287 , H01L29/732
摘要： A low-power high-frequency bipolar transistor is formed to have a small self-aligned base region that reduces the base-to-collector capacitance, and small self-aligned base and emitter contacts that reduce the base-to-emitter capacitance and the base resistance. The base and emitter contacts are formed to have sub-lithographic feature sizes.

37. 发明授权

US08704295B1 Schottky and MOSFET+Schottky structures, devices, and methods 有权
标题翻译：肖特基和MOSFET +肖特基结构，器件和方法
公开(公告)号：US08704295B1
公开(公告)日：2014-04-22
申请号：US13212044
申请日：2011-08-17
申请人： Mohamed N. Darwish , Jun Zeng , Richard A. Blanchard
发明人： Mohamed N. Darwish , Jun Zeng , Richard A. Blanchard
IPC分类号： H01L29/78
CPC分类号： H01L29/7806 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7813 , H01L29/872
摘要： Power devices which include trench Schottky barrier diodes and also (preferably) trench-gate transistors. Isolation trenches flank both the gate regions and the diode mesas, and have an additional diffusion below the bottom of the isolation trenches. The additional diffusion helps to reduce the electric field (and leakage), when the device is in the OFF state, at both the Schottky barrier and at the body diode.
摘要翻译：功率器件包括沟道肖特基势垒二极管和（优选）沟槽栅极晶体管。隔离沟槽面对栅极区域和二极管台面两侧，并且在隔离沟槽底部具有另外的扩散。当器件处于OFF状态时，附加扩散有助于在肖特基势垒和二极管二极管的同时减小电场（和泄漏）。

38. 发明授权

US08546878B2 Semiconductor device incorporating charge balancing 有权
标题翻译：并入电荷平衡的半导体器件
公开(公告)号：US08546878B2
公开(公告)日：2013-10-01
申请号：US13156848
申请日：2011-06-09
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L21/02164 , H01L21/0217 , H01L21/02321 , H01L21/2003 , H01L21/265 , H01L21/2658 , H01L21/26586 , H01L21/28008 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/823885 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4236 , H01L29/42368 , H01L29/66537 , H01L29/66666 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/7835
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.
摘要翻译：半导体器件包括形成在其上的第一导电类型的半导体层和第二导电类型的半导体层。第二导电类型的半导体层的特征在于第一厚度。半导体器件包括具有预定深度并延伸到第二导电类型的半导体层的一组沟槽，从而限定设置在第二导电类型的半导体层与每个沟槽之间的界面区域。沟槽包括基本上由布置在其中的介电材料组成的远端部分和包括电介质材料的近端部分和设置在沟槽的近端部分中的电介质材料内部的栅极材料。该半导体器件还包括耦合到第二导电类型的半导体层的源极区域。

39. 发明授权

US08330186B2 Lateral devices containing permanent charge 有权
标题翻译：包含永久充电的侧向装置
公开(公告)号：US08330186B2
公开(公告)日：2012-12-11
申请号：US12432917
申请日：2009-04-30
申请人： Mohamed N. Darwish , Amit Paul
发明人： Mohamed N. Darwish , Amit Paul
IPC分类号： H01L29/66
CPC分类号： H01L29/408 , H01L29/0634 , H01L29/0873 , H01L29/0886 , H01L29/42368 , H01L29/7816 , H01L29/7825 , H01L29/7835
摘要： A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.
摘要翻译：横向器件包括通过漂移层连接到漏极区的栅极区域。绝缘区域与栅极区域和漏极区域之间的漂移层相邻。永久电荷嵌入在绝缘区域中，足以在绝缘区域引起反转。

40. 发明申请

US20120098055A1 Power Semiconductor Devices, Structures, and Related Methods 有权
标题翻译：功率半导体器件，结构和相关方法
公开(公告)号：US20120098055A1
公开(公告)日：2012-04-26
申请号：US13175975
申请日：2011-07-05
申请人： Mohamed N. Darwish , Jun Zeng , Richard A. Blanchard
发明人： Mohamed N. Darwish , Jun Zeng , Richard A. Blanchard
IPC分类号： H01L29/78
CPC分类号： H01L29/7393 , H01L21/26586 , H01L29/0634 , H01L29/0873 , H01L29/0878 , H01L29/1095 , H01L29/167 , H01L29/402 , H01L29/407 , H01L29/408 , H01L29/41766 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/7816
摘要： Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.
摘要翻译：功率半导体器件和相关方法，其中多数载流子流被分成平行的流经两个相反导电类型的漂移区域。

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