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31. 发明授权

US6118163A Transistor with integrated poly/metal gate electrode 失效
标题翻译：具有集成多晶/金属栅电极的晶体管
公开(公告)号：US6118163A
公开(公告)日：2000-09-12
申请号：US17720
申请日：1998-02-04
申请人： Mark I. Gardner , Derick J. Wristers , Jon D. Cheek
发明人： Mark I. Gardner , Derick J. Wristers , Jon D. Cheek
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/28061 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： An integrated circuit transistor and method of making the same are provided. The transistor includes a substrate, first and second source/drain regions, and a gate electrode stack coupled to the substrate. The gate electrode stack is fabricated by forming a first insulating layer on the substrate, forming a first conductor layer on the first insulating layer, and forming a metal layer on the first conductor layer. A second insulating layer, such as an interlevel dielectric layer, is coupled to the substrate adjacent to the gate electrode stack. Sidewall spacers and LDD processing may be incorporated. The transistor and method integrate metal and polysilicon into a self-aligned gate electrode stack.
摘要翻译：提供集成电路晶体管及其制造方法。晶体管包括衬底，第一和第二源极/漏极区域以及耦合到衬底的栅电极堆叠。通过在基板上形成第一绝缘层，在第一绝缘层上形成第一导体层，在第一导体层上形成金属层，制作栅电极堆叠。诸如层间电介质层的第二绝缘层耦合到与栅电极堆叠相邻的衬底。可以并入侧壁间隔物和LDD处理。晶体管和方法将金属和多晶硅集成到自对准栅极电极堆叠中。

32. 发明授权

US6117760A Method of making a high density interconnect formation 失效
标题翻译：制造高密度互连结构的方法
公开(公告)号：US6117760A
公开(公告)日：2000-09-12
申请号：US968682
申请日：1997-11-12
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Fred N. Hause
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/528 , H01L21/4763
CPC分类号： H01L21/76885 , H01L21/76838 , H01L23/5283 , H01L2924/0002
摘要： A technique is provided for forming interconnects laterally spaced from each other across a semiconductor topography by a deposited dielectric spacer layer. The lateral distance between each interconnect is advantageously dictated by the thickness of the spacer layer rather than by the minimum feature size of a lithographically patterned masking layer. In an embodiment, a first and second conductive interconnects are formed a spaced distance apart upon a semiconductor topography. The first and second interconnects are defined using optical lithography and an etch technique. A dielectric layer is CVD deposited across the exposed surfaces of the first and second interconnects and of the semiconductor topography. The CVD deposition conditions are controlled so as to form a relatively thin spacers laterally adjacent the sidewalls of the interconnects. A conductive material is then deposited across into a trench arranged between the first and second interconnects, and CMP polished such that the upper surface of the conductive material is at an elevational level proximate that of the surfaces of the interconnects. A third interconnect is thereby formed within the trench laterally adjacent the first and second interconnects.
摘要翻译：提供了一种技术，用于通过沉积的介电隔离层在半导体形貌上形成横向间隔开的互连。每个互连之间的横向距离有利地由隔离层的厚度而不是光刻图案化掩模层的最小特征尺寸决定。在一个实施例中，第一和第二导电互连在半导体形貌上分开形成间隔距离。第一和第二互连使用光刻和蚀刻技术来定义。介电层是跨越第一和第二互连的暴露表面和半导体形貌的CVD沉积的。控制CVD沉积条件以形成横向邻近互连侧壁的较薄的间隔件。然后将导电材料沉积到布置在第一和第二互连之间的沟槽中，并且CMP抛光，使得导电材料的上表面处于靠近互连表面的上表面。因此，在沟槽内形成第三互连件，横向地邻近第一和第二互连。

33. 发明授权

US6114251A Method of fabrication for ultra thin nitride liner in silicon trench isolation 失效
标题翻译：硅沟隔离中超薄氮化物衬垫的制造方法
公开(公告)号：US6114251A
公开(公告)日：2000-09-05
申请号：US226024
申请日：1999-01-06
申请人： Thien T. Nguyen , Mark I. Gardner , Frederick N. Hause
发明人： Thien T. Nguyen , Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/311 , H01L21/762 , H01L21/3065
CPC分类号： H01L21/31116 , H01L21/76224
摘要： An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in the substrate and a first insulating layer in the trench that has a bottom, a first sidewall and a second sidewall. Silicon nitride is deposited in the trench. Silicon nitride is removed from the bottom of the first insulating layer to establish a layer of silicon nitride on the first and second sidewalls by performing a first plasma etch of the deposited silicon nitride with an ambient containing He, SF.sub.6, and HBr, and a second plasma etch with an ambient containing He, SF.sub.6, and HBr. An insulating material is deposited in the trench. The method provides for reliable manufacture of nitride liners for trench isolation structures. Scaling is enhanced and the potential for parasitic leakage current due to liner oxide fracture or irregularity is reduced.
摘要翻译：提供隔离结构及其制造方法。在一个方面，该方法包括以下步骤：在衬底中形成沟槽，在沟槽中形成第一绝缘层，该第一绝缘层具有底部，第一侧壁和第二侧壁。氮化硅沉积在沟槽中。从第一绝缘层的底部去除氮化硅，以通过对包含He，SF 6和HBr的环境进行沉积的氮化硅的第一等离子体蚀刻在第一和第二侧壁上建立氮化硅层，第二用含有He，SF6和HBr的环境进行等离子体蚀刻。绝缘材料沉积在沟槽中。该方法提供可靠地制造用于沟槽隔离结构的氮化物衬垫。缩放增加，并且由于衬垫氧化物断裂或不规则性引起的寄生漏电流的可能性降低。

34. 发明授权

US6111260A Method and apparatus for in situ anneal during ion implant 失效
标题翻译：离子注入过程中原位退火的方法和装置
公开(公告)号：US6111260A
公开(公告)日：2000-08-29
申请号：US872258
申请日：1997-06-10
申请人： Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01J37/317
CPC分类号： H01J37/3171 , H01J2237/316
摘要： During a semiconductor substrate ion implant process thermal energy is supplied to raise the temperature of the semiconductor wafer. The increased temperature of the semiconductor wafer during implantation acts to anneal the implanted impurities or dopants in the wafer, reducing impurity diffusion and reducing the number of fabrication process steps. An ion implant device includes an end station that is adapted for application and control of thermal energy to the end station for raising the temperature of a semiconductor substrate wafer during implantation. The adapted end station includes a heating element for heating the semiconductor substrate wafer, a thermocouple for sensing the temperature of the semiconductor substrate wafer, and a controller for monitoring the sensed temperature and controlling the thermal energy applied to the semiconductor substrate wafer by the heating element. An ion implant device including a system for applying and controlling thermal energy applied to a semiconductor substrate wafer during ion implantation raises the temperature of the wafer to a temperature that is sufficient to activate impurities within the semiconductor substrate wafer when an ion beam is implanting ions to the wafer, but the temperature is insufficient to activate impurities when the ion beam is inactive.
摘要翻译：在半导体衬底离子注入过程中，提供热能以提高半导体晶片的温度。在注入期间半导体晶片的温度升高期间用于退火晶片中注入的杂质或掺杂剂，减少杂质扩散并减少制造工艺步骤的数量。离子注入装置包括终端站，其适于向端站施加和控制热能，以在植入期间提高半导体衬底晶片的温度。适用的端站包括用于加热半导体衬底晶片的加热元件，用于感测半导体衬底晶片的温度的热电偶，以及用于监测感测温度并通过加热元件控制施加到半导体衬底晶片的热能的控制器。包括用于在离子注入期间施加和控制施加到半导体衬底晶片的热能的系统的离子注入装置将晶片的温度升高到当离子束注入离子时足以激活半导体衬底晶片内的杂质的温度晶片，但当离子束无效时，温度不足以激活杂质。

35. 发明授权

US6107129A Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance 失效
标题翻译：具有多个LDD和/或源极/漏极注入步骤以增强电路性能的集成电路
公开(公告)号：US6107129A
公开(公告)日：2000-08-22
申请号：US38511
申请日：1998-03-11
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L29/78 , H01L29/72
CPC分类号： H01L29/6659 , H01L29/7833 , H01L29/7835
摘要： An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.
摘要翻译：形成集成电路，由此产生提高集成电路总体速度的MOS晶体管结。晶体管结包括多个注入到结点的轻掺杂漏极（LDD）区域，结点的源极/漏极区域以及LDD和源极/漏极区域两者。多个植入物的第一植入物用于调节植入区域，使得第二和随后的植入物以相对高的浓度精确地放置在基底表面附近。因此，所得到的结是具有相对高的驱动强度，低接触电阻率，低的源到漏寄生电阻和相对低的结电容的结。

36. 发明授权

US6106618A Photoresist application for a circlet wafer 失效
标题翻译：光刻胶应用于圆盘片
公开(公告)号：US6106618A
公开(公告)日：2000-08-22
申请号：US88783
申请日：1998-06-01
申请人： Mark C. Gilmer , Mark I. Gardner
发明人： Mark C. Gilmer , Mark I. Gardner
IPC分类号： B05B9/04 , B05B13/02 , B05C9/14 , B05C11/08 , G03F7/16 , H01L21/00 , B05C11/02 , B05B3/02 , B05C9/06 , B05C13/00
CPC分类号： H01L21/6715 , B05B13/0228 , B05C11/08 , G03F7/162 , B05B9/0403 , B05C9/14
摘要： Apparatus and method for depositing fluids on both sides of a semiconductor wafer that has a central opening are provided. In one aspect, the apparatus includes a mandrel for holding the wafer and a motor coupled to the mandrel and that is operable to rotate the mandrel. The apparatus also includes means for dispensing a first volume of fluid on the semiconductor wafer and a second volume of fluid on the semiconductor wafer. According to the method, a semiconductor wafer is coupled to a rotatable mandrel. The mandrel is rotated to spin the semiconductor wafer and a semiconductor processing fluid is sprayed on the first and second sides of the semiconductor wafer.
摘要翻译：提供了用于在具有中心开口的半导体晶片的两侧上沉积流体的装置和方法。在一个方面，该装置包括用于保持晶片的心轴和联接到心轴的马达，并且可操作以用于旋转心轴。该装置还包括用于在半导体晶片上分配第一体积的流体的装置和半导体晶片上的第二体积的流体。根据该方法，将半导体晶片连接到可旋转心轴。旋转心轴以旋转半导体晶片，并且半导体处理流体喷射在半导体晶片的第一和第二侧上。

37. 发明授权

US6100148A Semiconductor device having a liner defining the depth of an active region, and fabrication thereof 失效
标题翻译：半导体器件具有限定有源区的深度的衬垫及其制造
公开(公告)号：US6100148A
公开(公告)日：2000-08-08
申请号：US995023
申请日：1997-12-19
申请人： Mark I. Gardner , Derick Wristers , Jim H. Fulford
发明人： Mark I. Gardner , Derick Wristers , Jim H. Fulford
IPC分类号： H01L21/265 , H01L21/336 , H01L29/06 , H01L29/10
CPC分类号： H01L29/6659 , H01L21/26506 , H01L29/0653 , H01L29/1083
摘要： A semiconductor device having a liner which defines the depth of an active region and a process for fabricating such a device is disclosed. The use of a liner can, for example, allow the formation of shallower source/drain regions and enhance the performance of the device. In accordance with one aspect of the process, a semiconductor device is formed by forming a gate electrode over a substrate and forming a liner in the substrate adjacent to the gate electrode. An active region is then formed in the substrate, whereby the depth of an active region is defined by the liner. The liner can be formed from several materials including, for example, n-type and p-type dopants and/or oxygen-bearing species.
摘要翻译：公开了一种具有限定有源区的深度的衬垫的半导体器件和用于制造这种器件的工艺。衬垫的使用可以例如允许形成更浅的源极/漏极区域并增强器件的性能。根据该方法的一个方面，通过在衬底上形成栅电极并在与栅电极相邻的衬底中形成衬垫来形成半导体器件。然后在衬底中形成有源区，由此衬里限定有源区的深度。衬垫可以由几种材料形成，包括例如n型和p型掺杂剂和/或含氧物质。

38. 发明授权

US6096591A Method of making an IGFET and a protected resistor with reduced processing steps 失效
标题翻译：制造IGFET和受保护电阻的方法，减少加工步骤
公开(公告)号：US6096591A
公开(公告)日：2000-08-01
申请号：US911746
申请日：1997-08-15
申请人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
发明人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/02 , H01L27/06 , H01L21/8234
CPC分类号： H01L28/20 , H01L27/0629
摘要： A method of making an IGFET and a protected resistor includes providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor region, forming an insulating layer over the gate and the diffused resistor, forming a masking layer over the insulating layer that covers the resistor region and includes an opening above the active region, applying an etch using the masking layer as an etch mask so that unetched portions of the insulating layer over the active region form spacers in close proximity to opposing sidewalls of the gate and an unetched portion of the insulating layer over the resistor region forms a resistor-protect insulator, and forming a source and a drain in the active region. In this manner, a single insulating layer provides both sidewall spacers for the gate and a resistor-protect insulator for the diffused resistor.
摘要翻译：制造IGFET和受保护电阻器的方法包括向半导体衬底提供有源区和电阻区，在有源区上形成栅极，在电阻区中形成扩散电阻，在栅极上形成绝缘层，扩散电阻器，在覆盖电阻器区域的绝缘层上形成掩模层，并且在有源区域上方包括开口，使用掩模层施加蚀刻作为蚀刻掩模，使得在有源区域上的绝缘层的未蚀刻部分形成间隔物靠近栅极的相对侧壁并且在电阻器区域上的绝缘层的未蚀刻部分形成电阻器保护绝缘体，并且在有源区域中形成源极和漏极。以这种方式，单个绝缘层提供用于栅极的两个侧壁间隔件和用于扩散电阻器的电阻保护绝缘体。

39. 发明授权

US6091105A Method of making a self-aligned dopant enhanced RTA MOSFET 失效
标题翻译：制造自对准掺杂剂RTA MOSFET的方法
公开(公告)号：US6091105A
公开(公告)日：2000-07-18
申请号：US50753
申请日：1998-03-30
申请人： Mark I. Gardner , H. Jim Fulford
发明人： Mark I. Gardner , H. Jim Fulford
IPC分类号： H01L21/336 , H01L29/78 , H01L29/72
CPC分类号： H01L29/66666 , H01L29/7827
摘要： An integrated circuit and a method of fabricating the same in a substrate are provided. A trench is formed in the substrate. The trench has a sidewall. A first insulating layer is formed on the sidewall. A gate electrode is formed on the first insulating layer. A first source/drain region is formed in the substrate and a second source/drain region is formed in the substrate. A first portion of the first source/drain region and a second portion of the second source/drain region are vertically spaced apart to define a channel region in the substrate. The process enables channel lengths to be set independent of the maximum resolution of the photolithographic system used to pattern the wafer. Very short channel lengths may be implemented.
摘要翻译：提供一种集成电路及其制造方法。在衬底中形成沟槽。沟槽有侧壁。在侧壁上形成第一绝缘层。在第一绝缘层上形成栅电极。在衬底中形成第一源极/漏极区域，并且在衬底中形成第二源极/漏极区域。第一源极/漏极区域的第一部分和第二源极/漏极区域的第二部分垂直间隔开以限定衬底中的沟道区域。该过程使得通道长度被设置为独立于用于图案化晶片的光刻系统的最大分辨率。可以实现非常短的通道长度。

40. 发明授权

US6090694A Local interconnect patterning and contact formation 失效
标题翻译：局部互连图案和接触形成
公开(公告)号：US6090694A
公开(公告)日：2000-07-18
申请号：US991742
申请日：1997-12-16
申请人： Fred N. Hause , Charles E. May , Mark I. Gardner
发明人： Fred N. Hause , Charles E. May , Mark I. Gardner
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/76832 , Y10S438/952
摘要： A method for forming a semiconductor device to produce a more distortion free via for interconnecting levels within a device or forming a connection between an external surface and an internal layer within a device includes the step of substituting a material similar to an etch stop adjacent one of the layers for the ARC. In other words, an etch stop is placed over the metal layer formed on a layer within the device. This is followed by a layer of silicon dioxide (SiO.sub.2) and then by a layer of material similar to the etch stop. Photoresist is placed on the layer of material similar to etch stop. The photoresist is exposed to light to form the location of the vias. The layer of material similar to etch stop, and the SiO.sub.2 layer are then removed in separate etching steps to form the via pathway from the resist to the etch stop adjacent the metal of the layer selected to be interconnected by the via. The resist can then be removed. This leaves the material similar to the etch stop located adjacent one surface of the SiO.sub.2 layer, and leaves the etch stop covering the metal in the via opening. One etch step can now be used to remove the etch stop covering the metal in the via opening and to remove the material similar to the etch stop located on the SiO.sub.2.
摘要翻译：用于形成半导体器件以产生用于在器件内互连电平或形成器件中的外表面和内部层之间的连接的无失真通孔的方法包括以下步骤：将与蚀刻停止相邻的材料 ARC的层。换句话说，蚀刻停止放置在形成在器件内的层上的金属层上。之后是二氧化硅层（SiO 2），然后是与蚀刻停止层相似的材料层。光刻胶放置在与蚀刻停止相似的材料层上。光致抗蚀剂暴露于光以形成通孔的位置。类似于蚀刻停止的材料层，然后在单独的蚀刻步骤中去除SiO 2层，以形成从抗蚀剂到蚀刻停止件的通孔路径，该蚀刻停止件邻近选定为由通孔相互连接的层的金属。然后可以除去抗蚀剂。这使得材料类似于位于SiO 2层的一个表面附近的蚀刻停止层，并且使蚀刻停止件覆盖通孔孔中的金属。现在可以使用一个蚀刻步骤去除覆盖通孔开口中的金属的蚀刻停止层，并且去除类似于位于SiO 2上的蚀刻停止层的材料。

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