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31. 发明申请

US20080191262A1 NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20080191262A1
公开(公告)日：2008-08-14
申请号：US11768179
申请日：2007-06-25
申请人： Ko-Hsing Chang , Chiu-Tsung Huang
发明人： Ko-Hsing Chang , Chiu-Tsung Huang
IPC分类号： H01L29/788 , H01L21/8246
CPC分类号： H01L29/792 , G11C16/0483 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/42336
摘要： The invention provides a non-volatile memory including a substrate, an active layer, device isolation layers and memory cells. The active layer disposed on the substrate protrudes from the substrate surface. Regarding the active layer, the device isolation layers are respectively disposed on the two sides thereof; the surface of the device isolation layers is lower than that of the active layer; the charge storage layer is disposed on the sidewalls thereof between the control gate and the active layer; the cap layer is disposed in the top section thereof between the control gate and the active layer, and the source/drain region is disposed in the active layer at the two sides of the control gate. Each of the memory cells includes a control gate, a charge storage layer, a cap layer and a source/drain region. The control gate disposed on the substrate crosses over the active layer.
摘要翻译：本发明提供一种非易失性存储器，其包括衬底，有源层，器件隔离层和存储器单元。设置在基板上的有源层从基板表面突出。关于有源层，器件隔离层分别设置在其两侧; 器件隔离层的表面低于有源层的表面; 电荷存储层设置在控制栅极和有源层之间的侧壁上; 盖层设置在控制栅极和有源层之间的顶部，并且源极/漏极区域设置在控制栅极两侧的有源层中。每个存储单元包括控制栅极，电荷存储层，盖层和源极/漏极区域。设置在基板上的控制栅极跨越有源层。

32. 发明授权

US07405124B2 Fabricating method of non-volatile memory 有权
标题翻译：非易失性存储器的制作方法
公开(公告)号：US07405124B2
公开(公告)日：2008-07-29
申请号：US11306384
申请日：2005-12-27
申请人： Ko-Hsing Chang
发明人： Ko-Hsing Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11519 , H01L27/11521
摘要： A method for fabricating a non-volatile memory is described. A substrate having isolation structures is provided. These isolation structures protrude from the substrate, and a first mask layer is formed on the substrate between the isolation structures. A second mask layer is formed on the substrate. The second and the first mask layers are patterned to form openings exposing part of the surface of the substrate and the isolation structures. A tunneling dielectric layer and a first conductive layer are formed on the substrate. The first conductive layer is filled in the opening, and is divided into blocks by the isolation structures, the second mask layer, and the first mask layer. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the substrate to fill up the openings. Doped regions are formed in the substrate on both sides of the second conductive layer.
摘要翻译：描述了制造非易失性存储器的方法。提供了具有隔离结构的基板。这些隔离结构从衬底突出，并且在隔离结构之间的衬底上形成第一掩模层。在基板上形成第二掩模层。将第二和第一掩模层图案化以形成露出衬底的表面部分和隔离结构的开口。隧道介电层和第一导电层形成在衬底上。第一导电层填充在开口中，并且通过隔离结构，第二掩模层和第一掩模层被分成块。在基板上形成栅极间电介质层。在基板上形成第二导电层以填充开口。掺杂区域形成在第二导电层的两侧的基板中。

33. 发明申请

US20070155087A1 METHOD OF MANUFACTURING SPLIT GATE FLASH MEMORY 审中-公开
标题翻译：制造分离栅闪存的方法
公开(公告)号：US20070155087A1
公开(公告)日：2007-07-05
申请号：US11683439
申请日：2007-03-08
申请人： Ko-Hsing Chang , Wu-Tsung Chung , Tsung-Cheng Huang
发明人： Ko-Hsing Chang , Wu-Tsung Chung , Tsung-Cheng Huang
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114 , H01L29/42324 , H01L29/7885
摘要： A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.
摘要翻译：提供了分闸门闪存。在衬底中形成沟槽以限定活性层。器件隔离层形成在沟槽中。器件隔离层的表面低于有源层的表面。在有源层上形成各自包括隧道电介质层，浮栅和覆盖层的层叠栅极结构。栅极间电介质层形成在堆叠的栅极结构的侧壁上。选择栅极形成在层叠的栅极结构的一侧并跨越有源层。选择栅极电介质层形成在选择栅极和有源层之间。源极区域形成在堆叠栅极结构的另一侧上的有源层中。漏极区域形成在选择栅极一侧的有源层中。

34. 发明授权

US07098109B2 Multi-level memory cell and fabricating method thereof 失效
标题翻译：多层存储单元及其制造方法
公开(公告)号：US07098109B2
公开(公告)日：2006-08-29
申请号：US11160523
申请日：2005-06-28
申请人： Chiu-Tsung Huang , Ko-Hsing Chang
发明人： Chiu-Tsung Huang , Ko-Hsing Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/7923
摘要： A multi-level memory cell includes a substrate, an insulation layer, a silicon stripe, a first control gate, a second control gate, source/drain regions, silicon oxide/silicon nitride/silicon oxide composite layers. The insulation layer and the silicon stripe are sequentially disposed on the substrate. The first control gate and the second control gate are respectively disposed on the sidewalls of the silicon stripe, while the source/drain regions are configured in the silicon stripe beside both sides of the first control gate and the second control gate. The composite dielectric layers are disposed between the first control gate and the silicon stripe, and between the second control gate and the silicon stripe. Since a single memory structure can store a multiple bit of information, it is advantageous for minimizing devices.
摘要翻译：多层存储单元包括衬底，绝缘层，硅条，第一控制栅极，第二控制栅极，源极/漏极区域，氧化硅/氮化硅/氧化硅复合层。绝缘层和硅条依次设置在基板上。第一控制栅极和第二控制栅极分别设置在硅条的侧壁上，而源极/漏极区域配置在除了第一控制栅极和第二控制栅极两侧的硅条纹之外。复合电介质层设置在第一控制栅极和硅条之间以及第二控制栅极和硅条之间。由于单个存储器结构可以存储多个位的信息，所以最小化器件是有利的。

35. 发明申请

US20050233519A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20050233519A1
公开(公告)日：2005-10-20
申请号：US10905610
申请日：2005-01-12
申请人： Ko-Hsing Chang , Chiu-Tsung Huang
发明人： Ko-Hsing Chang , Chiu-Tsung Huang
IPC分类号： H01L21/02 , H01L21/4763 , H01L21/76 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/7681 , H01L21/76802 , H01L21/76808 , H01L23/5223 , H01L23/5226 , H01L23/53295 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device. The method comprises steps of providing a substrate having a first metal layer and a second metal layer formed thereon. A first dielectric layer, an etching stop layer having a first opening located above the first metal layer and a second opening located above the second metal layer and a second dielectric layer are formed sequentially. A portion of the first dielectric layer and a portion of the second dielectric layer are removed to form a first trench exposing the first metal layer. A capacitor dielectric layer is formed over the substrate. A third opening is formed in the capacitor dielectric layer. A portion of the second dielectric layer and a portion of the first dielectric layer exposed by the third opening are removed to form an opening. A metal layer is formed to fill out the first trench and the opening.
摘要翻译：一种制造半导体器件的方法。该方法包括提供具有形成在其上的第一金属层和第二金属层的基板的步骤。顺序地形成第一电介质层，具有位于第一金属层上方的第一开口和位于第二金属层上方的第二开口的蚀刻停止层和第二介电层。去除第一电介质层的一部分和第二电介质层的一部分以形成露出第一金属层的第一沟槽。在衬底上形成电容器电介质层。在电容器电介质层中形成第三开口。第二电介质层的一部分和被第三开口暴露的第一电介质层的一部分被去除以形成开口。形成金属层以填充第一沟槽和开口。

36. 发明申请

US20050227443A1 MULTI-LEVEL MEMORY CELL AND FABRICATING METHOD THEREOF 失效
标题翻译：多层记忆体及其制作方法
公开(公告)号：US20050227443A1
公开(公告)日：2005-10-13
申请号：US11160523
申请日：2005-06-28
申请人： Chiu-Tsung Huang , Ko-Hsing Chang
发明人： Chiu-Tsung Huang , Ko-Hsing Chang
IPC分类号： H01L21/28 , H01L21/336 , H01L29/792 , H01L21/8239
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/7923
摘要： A multi-level memory cell includes a substrate, an insulation layer, a silicon stripe, a first control gate, a second control gate, source/drain regions, silicon oxide/silicon nitride/silicon oxide composite layers. The insulation layer and the silicon stripe are sequentially disposed on the substrate. The first control gate and the second control gate are respectively disposed on the sidewalls of the silicon stripe, while the source/drain regions are configured in the silicon stripe beside both sides of the first control gate and the second control gate. The composite dielectric layers are disposed between the first control gate and the silicon stripe, and between the second control gate and the silicon stripe. Since a single memory structure can store a multiple bit of information, it is advantageous for minimizing devices.
摘要翻译：多层存储单元包括衬底，绝缘层，硅条，第一控制栅极，第二控制栅极，源极/漏极区域，氧化硅/氮化硅/氧化硅复合层。绝缘层和硅条依次设置在基板上。第一控制栅极和第二控制栅极分别设置在硅条的侧壁上，而源极/漏极区域配置在除了第一控制栅极和第二控制栅极两侧的硅条纹之外。复合电介质层设置在第一控制栅极和硅条之间以及第二控制栅极和硅条之间。由于单个存储器结构可以存储多个位的信息，所以最小化器件是有利的。

37. 发明申请

US20050145921A1 [NON-VOLATILE MEMORY CELL AND MANUFACTURING METHOD THEREOF] 失效
标题翻译： [非易失性存储单元及其制造方法]
公开(公告)号：US20050145921A1
公开(公告)日：2005-07-07
申请号：US10709372
申请日：2004-04-30
申请人： Ko-Hsing Chang , Chiu-Tsung Huang
发明人： Ko-Hsing Chang , Chiu-Tsung Huang
IPC分类号： H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7926
摘要： A non-volatile memory cell is provided. The non-volatile memory at least includes a substrate, a gate, a first source/drain region, a composite dielectric layer and a second source/drain region. A trench is formed in a substrate and a gate is formed inside the trench. The first source/drain region is formed at the bottom of the trench. The composite dielectric layer is formed between the gate and the surface of the trench. The composite dielectric layer includes at least a charge-trapping layer. The second source/drain region is formed in the substrate next to the sides of the gate.
摘要翻译：提供非易失性存储单元。非易失性存储器至少包括衬底，栅极，第一源极/漏极区域，复合电介质层和第二源极/漏极区域。在衬底中形成沟槽，并且在沟槽内形成栅极。第一源极/漏极区域形成在沟槽的底部。复合电介质层形成在沟槽的栅极和表面之间。复合介电层至少包括电荷捕获层。第二源极/漏极区域形成在栅极侧面旁边的基板中。

38. 发明授权

US06870212B2 Trench flash memory device and method of fabricating thereof 有权
标题翻译：沟槽式闪存装置及其制造方法
公开(公告)号：US06870212B2
公开(公告)日：2005-03-22
申请号：US10065345
申请日：2002-10-07
申请人： Ko-Hsing Chang , Chih-Wei Hung
发明人： Ko-Hsing Chang , Chih-Wei Hung
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/76
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L27/11556
摘要： A method of fabricating a trench flash memory device, where the method includes forming a patterned mask layer on the substrate and using it as the mask for form a trench in the substrate. Next, a source region is formed in the substrate near the bottom of the trench, followed by forming a tunnel oxide layer, a floating gate, a gate dielectric layer and a control in the trench. After removing the mask layer to expose the substrate, a drain region is further formed in the substrate. In this invention, since the trench flash memory device has a cylindrical shape with the tunnel oxide layer, the floating gate and the gate dielectric layer wrapping around the control gate, the overlap area between the floating gate and the control gate is increased, resulting in a higher gate coupling rate (GCR), a lower required operation voltage and a higher device operation speed and efficiency.
摘要翻译：一种制造沟槽闪速存储器件的方法，其中所述方法包括在衬底上形成图案化掩模层并将其用作在衬底中形成沟槽的掩模。接下来，在沟槽的底部附近的衬底中形成源极区，然后在沟槽中形成隧道氧化物层，浮栅，栅极电介质层和控制。在去除掩模层以露出衬底之后，在衬底中进一步形成漏区。在本发明中，由于沟槽式闪速存储器件具有隧道氧化层的圆柱形状，浮动栅极和围绕控制栅极的栅介质层，所以浮栅和控制栅之间的重叠面积增加，导致更高的栅极耦合速率（GCR），较低的所需工作电压和更高的器件操作速度和效率。

39. 发明授权

US06768162B1 Split gate flash memory cell and manufacturing method thereof 有权
公开(公告)号：US06768162B1
公开(公告)日：2004-07-27
申请号：US10604612
申请日：2003-08-05
申请人： Ko-Hsing Chang , Hann-Jye Hsu
发明人： Ko-Hsing Chang , Hann-Jye Hsu
IPC分类号： H01L29788
CPC分类号： H01L27/11553 , H01L27/11556 , H01L29/42324 , H01L29/7883
摘要： A split gate flash memory cell includes a substrate having a trench, a stack structure disposed on the substrate, wherein the stack structure includes a tunneling dielectric layer, a floating gate and a cap layer; a first inter-gate dielectric layer and a second inter-gate dielectric layer disposed on the sidewalls of the stack structure, wherein the first inter-gate dielectric layer is contiguous to the top of the trench; a selective gate disposed on the sidwalls of the first inter-gate dielectric layer and the trench; a selective gate dielectric layer disposed between the selective gate and the substrate; a source region configured in the substrate beside the side of the stack structure with the second inter-gate dielectric layer; and a drain region configured at the bottom of the trench beside one side of the selective gate.

40. 发明授权

US6143606A Method for manufacturing split-gate flash memory cell 失效
标题翻译：分闸式闪存单元的制造方法
公开(公告)号：US6143606A
公开(公告)日：2000-11-07
申请号：US61618
申请日：1998-04-16
申请人： Ling-Sung Wang , Ko-Hsing Chang
发明人： Ling-Sung Wang , Ko-Hsing Chang
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336 , H01L21/4763
CPC分类号： H01L27/115 , H01L27/11521
摘要： In this method for manufacturing a split-gate flash memory cell, a floating gate and a control gate are formed over a substrate, and then first spacers are formed on the sidewalls of the gate structure. Next, a polysilicon layer is deposited over the gate structure and the substrate, and second spacers are formed on the sidewalls of the polysilicon layer. A self-aligned ion implantation process is performed, using the second spacers as a mask, implanting ions into the semiconductor substrate to form a drain region. This maintains the channel length. After removing the second spacers, another ion implantation process is performed to create a source region in the semiconductor substrate. During the second implantation, the polysilicon layer offers some protection for the semiconductor substrate, maintaining the capacity for tunneling. Finally, a conductive layer is formed over the polysilicon layer, and the conductive layer combined with the polysilicon layer forms the select gate.
摘要翻译：在用于制造分离栅极闪存单元的方法中，在衬底上形成浮栅和控制栅极，然后在栅极结构的侧壁上形成第一间隔物。接下来，在栅极结构和衬底上沉积多晶硅层，并且在多晶硅层的侧壁上形成第二间隔物。执行自对准离子注入工艺，使用第二间隔物作为掩模，将离子注入到半导体衬底中以形成漏极区。这保持通道长度。在去除第二间隔物之后，执行另一离子注入工艺以在半导体衬底中产生源区。在第二次注入期间，多晶硅层为半导体衬底提供了一些保护，保持了隧道的容量。最后，在多晶硅层上形成导电层，与多晶硅层结合的导电层形成选择栅极。

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