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31. 发明申请

US20100073998A1 DATA WRITING METHOD FOR MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC MEMORY 有权
标题翻译：磁阻效应元件和磁记忆的数据写入方法
公开(公告)号：US20100073998A1
公开(公告)日：2010-03-25
申请号：US12561495
申请日：2009-09-17
申请人： Masahiko NAKAYAMA , Hisanori Aikawa , Tsuneo Inaba , Kenji Tsuchida , Sumio Ikegawa , Hiroaki Yoda , Naoharu Shimomura
发明人： Masahiko NAKAYAMA , Hisanori Aikawa , Tsuneo Inaba , Kenji Tsuchida , Sumio Ikegawa , Hiroaki Yoda , Naoharu Shimomura
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1675
摘要： A data writing method for a magnetoresistive effect element of an aspect of the present invention including generating a write current in which a falling period from the start of a falling edge to the end of the falling edge is longer than a rising period from the start of a rising edge to the end of the rising edge, and flowing the write current through the magnetoresistive effect element which comprises a first magnetic layer having an invariable magnetizing direction, a second magnetic layer having a variable magnetizing direction, and a tunnel barrier layer provided between the first magnetic layer and the second magnetic layer, to change the magnetizing direction of the second magnetic layer.
摘要翻译：一种用于本发明一个方面的磁阻效应元件的数据写入方法，包括产生写入电流，其中从下降沿开始到下降沿结束的下降周期长于从开始上升沿到上升沿结束，并且使写入电流流过磁阻效应元件，该磁阻效应元件包括具有不变磁化方向的第一磁性层，具有可变磁化方向的第二磁性层和设置在可变磁化方向之间的隧道势垒层，第一磁性层和第二磁性层，以改变第二磁性层的磁化方向。

32. 发明申请

US20100072530A1 MAGNETIC RANDOM ACCESS MEMORTY 有权
标题翻译：磁性随机存取记忆
公开(公告)号：US20100072530A1
公开(公告)日：2010-03-25
申请号：US12627616
申请日：2009-11-30
申请人： Ryousuke Takizawa , Kenji Tsuchida
发明人： Ryousuke Takizawa , Kenji Tsuchida
IPC分类号： H01L29/82
CPC分类号： H01L27/228 , G11C11/1659 , G11C11/1675
摘要： A magnetic random access memory of an aspect of the present invention including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed and recording layers, wherein the magnetization directions of the fixed and recording layers are in a parallel state or in an anti-parallel state depending on a direction of a current flowing between the fixed and recording layers, a first transistor having a gate and a first current path having one end connected to the fixed layer, a second transistor having a gate and a second current path having one end connected to the recording layer, a first bit line to which other end of the first current path is connected, and a second bit line to which other end of the second current path is connected.
摘要翻译：本发明的磁性随机存取存储器包括具有固定磁化方向的固定层的磁阻效应元件，其磁化方向可逆的记录层和设置在固定层和记录层之间的非磁性层，其中固定记录层和记录层的磁化方向根据在固定层和记录层之间流过的电流的方向处于平行状态或反平行状态，具有栅极和第一电流通路的第一晶体管具有一个端部连接到固定层，第二晶体管具有栅极和第二电流路径，其一端连接到记录层，第一电流路径的另一端连接到第一位线和第二位线，第二位线连接第二电流路径的另一端。

33. 发明申请

US20090201717A1 RESISTANCE-CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20090201717A1
公开(公告)日：2009-08-13
申请号：US12366396
申请日：2009-02-05
申请人： Takashi MAEDA , Yoshihiro UEDA , Kenji TSUCHIDA
发明人： Takashi MAEDA , Yoshihiro UEDA , Kenji TSUCHIDA
IPC分类号： G11C11/00 , G11C11/416
CPC分类号： G11C11/1653 , G11C11/1673 , G11C11/1675
摘要： A resistance-change memory includes first and second bit lines running in the same direction, a third bit line running parallel to the first and second bit lines, fourth and fifth bit lines running in the same direction, a sixth bit line running parallel to the fourth and fifth bit lines, a first memory element which has one and the other terminals connected to the first and third bit lines, and changes to one of first and second resistance states, a first reference element having one and the other terminals connected to the fourth and sixth bit lines, and set in the first resistance state, a second reference element having one and the other terminals connected to the fifth and sixth bit lines, and set in the second resistance state, and a sense amplifier having first and second input terminals connected to the first and fourth bit lines.
摘要翻译：电阻变化存储器包括沿相同方向运行的第一和第二位线，与第一和第二位线并行运行的第三位线，沿相同方向运行的第四和第五位线，平行于第一位线的第六位线第四和第五位线，第一存储器元件，其具有连接到第一和第三位线的一个端子和另一个端子，并且改变为第一和第二电阻状态中的一个;第一参考元件，其中一个和另一个端子连接到第四和第六位线，并且设置在第一电阻状态，第二参考元件，其中一个和另一个端子连接到第五和第六位线，并被设置在第二电阻状态，以及读出放大器，具有第一和第二输入连接到第一和第四位线的端子。

34. 发明授权

US07529120B2 Semiconductor memory with resistance change element 失效
标题翻译：具有电阻变化元件的半导体存储器
公开(公告)号：US07529120B2
公开(公告)日：2009-05-05
申请号：US11480848
申请日：2006-07-06
申请人： Kenji Tsuchida
发明人： Kenji Tsuchida
IPC分类号： G11C11/00
CPC分类号： G11C29/808 , G11C11/16
摘要： A semiconductor memory includes a memory cell as a resistance change element and a switching element which are connected in series and a read word line connected to a control terminal of the switching element. In addition, the semiconductor memory includes a circuit which executes an auto-close operation for causing which makes a read word line RWL to be subjected to non-activation automatically after a fixed period from start of a read operation.
摘要翻译：半导体存储器包括作为电阻变化元件的存储单元和串联连接的开关元件和连接到开关元件的控制端子的读字线。此外，半导体存储器包括执行自动关闭操作的电路，该电路使读取字线RWL在从读取操作开始的固定时间段之后自动进行非激活。

35. 发明授权

US07471549B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07471549B2
公开(公告)日：2008-12-30
申请号：US11390254
申请日：2006-03-28
申请人： Tsuneo Inaba , Kenji Tsuchida , Yoshiaki Fukuzumi
发明人： Tsuneo Inaba , Kenji Tsuchida , Yoshiaki Fukuzumi
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A semiconductor memory device includes a write line, at least three first data-writing circuits which are connected to the write line, and memory cells which include a magnetoresistive element, are connected electrically and/or magnetically to the write line, and are arranged between the first data-writing circuits.
摘要翻译：半导体存储器件包括写入线，连接到写入线的至少三个第一数据写入电路和包括磁阻元件的存储器单元电和/或磁性地连接到写入线，并且被布置在第一个数据写入电路。

36. 发明授权

US06862210B2 Magnetic random access memory for storing information utilizing magneto-resistive effects 失效
标题翻译：磁性随机存取存储器，用于使用磁阻效应存储信息
公开(公告)号：US06862210B2
公开(公告)日：2005-03-01
申请号：US10422971
申请日：2003-04-25
申请人： Kenji Tsuchida , Yoshihisa Iwata , Tomoki Higashi
发明人： Kenji Tsuchida , Yoshihisa Iwata , Tomoki Higashi
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/00
CPC分类号： G11C11/15
摘要： A memory cell comprises a magneto-resistive element of which electrical resistance value varies with magnetism. A sub-bit line is connected to one end of the memory cell. A main-bit line is connected to the sub-bit line via a first selection circuit. A sense-amplifier is connected to the main-bit line via a second selection circuit. A wiring line is connected to the other end of the memory cell and arranged in a first direction. A first operation circuit is connected to one end of the wiring line via a third selection circuit. A second operation circuit is connected to the other end of the wiring line. A word line passes over an intersection between the memory cell and the wiring line and is arranged in a second direction perpendicular to the first direction.
摘要翻译：存储单元包括电阻值随磁力而变化的磁阻元件。子位线连接到存储单元的一端。主位线经由第一选择电路连接到子位线。读出放大器经由第二选择电路连接到主位线。布线沿着第一方向与存储单元的另一端连接。第一操作电路经由第三选择电路连接到布线的一端。第二操作电路连接到布线的另一端。字线通过存储单元和布线之间的交叉点，并且布置在垂直于第一方向的第二方向上。

37. 发明授权

US06753695B2 Semiconductor integrated circuit device and pulse width changing circuit 失效
标题翻译：半导体集成电路器件和脉冲宽度变化电路
公开(公告)号：US06753695B2
公开(公告)日：2004-06-22
申请号：US10104069
申请日：2002-03-25
申请人： Haruki Toda , Kenji Tsuchida , Satoshi Eto , Kuninori Kawabata
发明人： Haruki Toda , Kenji Tsuchida , Satoshi Eto , Kuninori Kawabata
IPC分类号： H03K3017
CPC分类号： H03K5/13 , H03K5/06 , H03K5/08
摘要： A semiconductor integrated circuit device comprises a plurality of MIS transistors, and an integrated circuit unit including logic gate circuits configured by a combination of the plurality of MIS transistors. Each of the MIS transistors has a gate including a circuit element represented by an equivalent circuit in which a capacitance and resistance are parallel-connected.
摘要翻译：半导体集成电路器件包括多个MIS晶体管，以及集成电路单元，其包括由多个MIS晶体管的组合构成的逻辑门电路。每个MIS晶体管具有包括由电容和电阻并联连接的等效电路表示的电路元件的栅极。

38. 发明授权

US06650590B2 Semiconductor memory device with reduced its chip area and power consumption 有权
公开(公告)号：US06650590B2
公开(公告)日：2003-11-18
申请号：US10103141
申请日：2002-03-22
申请人： Tsuneo Inaba , Fumihiro Kohno , Kenji Tsuchida , Toshimi Ikeda
发明人： Tsuneo Inaba , Fumihiro Kohno , Kenji Tsuchida , Toshimi Ikeda
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C8/14
摘要： One (first level shift circuit) of first and second level shift circuits is provided in a local word-drive-line driving circuit located near memory cell arrays. The second level shift circuit is provided in a global word-drive-line driving circuit located remote from the memory cell arrays.

39. 发明授权

US06615309B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06615309B2
公开(公告)日：2003-09-02
申请号：US10337977
申请日：2003-01-08
申请人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
发明人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
IPC分类号： G06F1202
CPC分类号： G11C7/22 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.
摘要翻译：半导体存储器件。该设备包括位线，耦合到位线的存储单元，耦合到存储单元的字线。为了从存储单元读取数据和读取操作的开始，读取操作的读取命令的第一次与在写入操作的写入命令的接收之间的第二时间不同，以便写入数据到存储单元和写入操作的开始。

40. 发明授权

US06608514B1 Clock signal generator circuit and semiconductor integrated circuit with the same circuit 失效
标题翻译：时钟信号发生器电路和半导体集成电路具有相同的电路
公开(公告)号：US06608514B1
公开(公告)日：2003-08-19
申请号：US09511352
申请日：2000-02-23
申请人： Hironobu Akita , Katsuaki Isobe , Masaharu Wada , Kenji Tsuchida , Haruki Toda
发明人： Hironobu Akita , Katsuaki Isobe , Masaharu Wada , Kenji Tsuchida , Haruki Toda
IPC分类号： H03K300
CPC分类号： G11C7/222 , G11C7/22 , H03K5/00006 , H03K5/135
摘要： A clock signal generator circuit comprises an off-chip driver, a first clock control circuit for outputting a first internal clock signal Tu synchronizing with an external clock signal CK, a second clock control circuit for outputting a second internal clock signal Td 180° out-of-phase with the external clock signal CK, a third clock control circuit for outputting a third internal clock signal aTx1 synchronizing with the first clock signal Tu and advanced in phase by at least the signal delay time in the off-chip driver, a fourth clock control circuit for outputting a fourth internal clock signal aTx2 synchronizing with the second clock signal Td and advanced in phase by at least the signal delay time in the off-chip driver, an OR circuit to which the third and fourth internal clock signals aTx1, aTx2 are inputted and which outputs a fifth internal clock signal aTx, and a fifth clock control circuit for outputting a sixth internal clock signal Tx which is in synchronization with the fifth internal clock signal aTx outputted from the OR circuit, has twice the frequency of the external clock signal CK, and is advanced in phase by the signal delay time in the off-chip driver.
摘要翻译：时钟信号发生器电路包括片外驱动器，用于输出与外部时钟信号CK同步的第一内部时钟信号Tu的第一时钟控制电路，用于将第二内部时钟信号Td 180°输出的第二时钟控制电路，与外部时钟信号CK的同相;第三时钟控制电路，用于输出与第一时钟信号Tu同步的第三内部时钟信号aTx1并至少在芯片外驱动器中的信号延迟时间相位前进;第四时钟控制电路，时钟控制电路，用于输出与第二时钟信号Td同步的第四内部时钟信号aTx2并至少在片外驱动器中的信号延迟时间相位前进;第三和第四内部时钟信号aTx1，输入aTx2并输出第五内部时钟信号aTx，以及第五时钟控制电路，用于输出与f同步的第六内部时钟信号Tx 从OR电路输出的第四内部时钟信号aTx具有外部时钟信号CK的两倍频率，并且在片外驱动器中相位提前信号延迟时间。

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