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31. 发明申请

US20100289084A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100289084A1
公开(公告)日：2010-11-18
申请号：US12777683
申请日：2010-05-11
申请人： Hong Sik Yoon , Jinshi Zhao , Ingyu Baek , Hyun Jun Sim , Minyoung Park
发明人： Hong Sik Yoon , Jinshi Zhao , Ingyu Baek , Hyun Jun Sim , Minyoung Park
IPC分类号： H01L29/78
CPC分类号： H01L27/228 , H01L27/0207 , H01L27/2454 , H01L27/249
摘要： Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.
摘要翻译：提供了一种半导体存储器件。半导体存储器件可以包括在基本上垂直于半导体衬底的上表面的方向上延伸的局部位线和与局部位线相交的局部字线。局部位线电连接到贯穿位线晶体管的栅极的位线通道柱，并且本地字线电连接到贯穿字线晶体管的栅极的字线通道柱。

32. 发明申请

US20100264544A1 Device including contact structure and method of forming the same 失效
标题翻译：包括接触结构的装置及其形成方法
公开(公告)号：US20100264544A1
公开(公告)日：2010-10-21
申请号：US11655116
申请日：2007-01-19
申请人： Jang-Eun Heo , Young-Moon Choi , Sun-Woo Lee , Hong-Sik Yoon , Kyung-Rae Byun
发明人： Jang-Eun Heo , Young-Moon Choi , Sun-Woo Lee , Hong-Sik Yoon , Kyung-Rae Byun
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76843 , H01L21/31116 , H01L21/3212 , H01L21/76823 , H01L21/76825 , H01L21/76831 , H01L21/76867 , H01L21/76876 , H01L21/76879 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , H01L2924/00
摘要： A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.
摘要翻译：一种器件包括在具有下导电图案的衬底上的绝缘层，所述绝缘层具有穿透绝缘层并暴露一部分下导电图案的接触孔，催化图案具有第一部分在暴露部分上下导电图案和接触孔的侧壁上的第二部分，在接触孔的侧壁上的间隔件，其中催化剂图案的第二部分设置在间隔件和侧壁之间，接触插塞在接触孔中并使催化剂图案接触，所述接触塞是碳纳米管材料。

33. 发明授权

US07795659B2 DRAM device and method of manufacturing the same 失效
标题翻译： DRAM装置及其制造方法
公开(公告)号：US07795659B2
公开(公告)日：2010-09-14
申请号：US12149406
申请日：2008-05-01
申请人： Hong-Sik Yoon , In-Seok Yeo , Seung-Jae Baik , Zong-Liang Huo , Shi-Eun Kim
发明人： Hong-Sik Yoon , In-Seok Yeo , Seung-Jae Baik , Zong-Liang Huo , Shi-Eun Kim
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10873 , H01L27/10829
摘要： In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.
摘要翻译：在DRAM器件及其制造方法中，提供了多隧道结（MTJ）结构，其包括彼此交替堆叠的导电图案和非导电图案。非导电图案具有比导电图案的带隙大的带隙。在MTJ结构的侧壁上形成栅极绝缘层和栅电极。字线与MTJ结构连接，位线与MTJ结构的顶面和底面之一连接。电容器与MTJ结构的一个顶表面和底表面连接，不与位线连接。 DRAM器件中的电流泄漏减少，并且单元电池可以垂直地堆叠在衬底上，因此DRAM器件需要较小的衬底表面积。

34. 发明申请

US20100136226A1 Methods of Forming Carbon Nanotubes 有权
标题翻译：形成碳纳米管的方法
公开(公告)号：US20100136226A1
公开(公告)日：2010-06-03
申请号：US12625896
申请日：2009-11-25
申请人： Xiaofeng Wang , Hong-Sik Yoon , In-Seok Yeo
发明人： Xiaofeng Wang , Hong-Sik Yoon , In-Seok Yeo
IPC分类号： B05D5/12
CPC分类号： C23C16/0281 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C23C16/26 , H01L51/0002 , H01L51/0048
摘要： Methods of forming carbon nanotubes include forming a catalytic metal layer on a sidewall of an electrically conductive region, such as a metal or metal nitride pattern. A plurality of carbon nanotubes are grown from the catalytic metal layer. These carbon nanotubes can be grown from a sidewall of the catalytic metal layer. The plurality of carbon nanotubes are then exposed to an organic solvent. This step of exposing the carbon nanotubes to the organic solvent may be preceded by a step of applying centrifugal forces to the plurality of carbon nanotubes. Alternatively, the exposing step may include applying a centrifugal force to the plurality of carbon nanotubes while simultaneously exposing the plurality of carbon nanotubes to an organic solvent.
摘要翻译：形成碳纳米管的方法包括在诸如金属或金属氮化物图案的导电区域的侧壁上形成催化金属层。从催化金属层生长多个碳纳米管。这些碳纳米管可以从催化金属层的侧壁生长。然后将多个碳纳米管暴露于有机溶剂。之前将碳纳米管暴露于有机溶剂的步骤之前可以将离心力施加到多个碳纳米管。或者，曝光步骤可以包括向多个碳纳米管施加离心力，同时将多个碳纳米管暴露于有机溶剂。

35. 发明申请

US20080138991A1 METHOD OF MANUFACTURING A TRANSISTOR 失效
标题翻译：制造晶体管的方法
公开(公告)号：US20080138991A1
公开(公告)日：2008-06-12
申请号：US11932994
申请日：2007-10-31
申请人： Hong Cho , Seung-Pil Chung , Hong-Sik Yoon , Kyung-Rae Byun
发明人： Hong Cho , Seung-Pil Chung , Hong-Sik Yoon , Kyung-Rae Byun
IPC分类号： H01L21/308 , H01L21/465
CPC分类号： H01L51/057 , B82Y10/00 , H01L51/0048 , Y10T29/49105
摘要： A multilayer insulating structure including a first stop layer, a first insulating layer and a second stop layer is formed on the first conductive structure. A second conductive structure and a second insulating layer are formed on the first conductive structure. The second insulating layer and the second conductive structure are etched to form a first hole and a second hole having a first radius. A spacer is formed on sidewalls of the first and second holes. The second stop layer and the first insulating layer are etched using the spacer as an etch mask to form a third hole having a second radius smaller than the first radius. A sacrificial filler is formed on the first stop layer to fill the third hole. After removing the spacer, the sacrificial filler is removed. The first stop layer is etched. A carbon nano-tube is grown from the first conductive structure.
摘要翻译：在第一导电结构上形成包括第一阻挡层，第一绝缘层和第二阻挡层的多层绝缘结构。在第一导电结构上形成第二导电结构和第二绝缘层。蚀刻第二绝缘层和第二导电结构以形成具有第一半径的第一孔和第二孔。间隔件形成在第一孔和第二孔的侧壁上。使用间隔物作为蚀刻掩模蚀刻第二阻挡层和第一绝缘层，以形成具有小于第一半径的第二半径的第三孔。在第一停止层上形成牺牲填料以填充第三孔。去除间隔物后，去除牺牲填料。第一个停止层被蚀刻。从第一导电结构生长碳纳米管。

36. 发明申请

US20080128802A1 SINGLE TRANSISTOR FLOATING BODY DRAM CELL HAVING RECESS CHANNEL TRANSISTOR STRUCTURE 审中-公开
标题翻译：具有输入通道晶体管结构的单晶片浮动体
公开(公告)号：US20080128802A1
公开(公告)日：2008-06-05
申请号：US12013547
申请日：2008-01-14
申请人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
发明人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
IPC分类号： H01L29/786
CPC分类号： H01L27/108 , H01L27/10802 , H01L29/7841 , H01L29/78648
摘要： Single transistor floating body dynamic random access memory (DRAM) cells include a semiconductor substrate and a barrier layer on the semiconductor substrate and a recess channel transistor on the barrier layer. The recess channel transistor includes a source region of a first conductivity type, a drain region of the first conductivity type spaced apart from the source region and a floating body of a second conductivity type between the barrier layer and the source region and the drain region. The floating body includes a recess region between the source region and the drain region.
摘要翻译：单晶体管浮体动态随机存取存储器（DRAM）单元包括半导体衬底和半导体衬底上的阻挡层以及阻挡层上的凹槽通道晶体管。凹槽沟道晶体管包括第一导电类型的源极区域，与源极区域隔开的第一导电类型的漏极区域和在阻挡层与源极区域和漏极区域之间的第二导电类型的浮动体。浮体包括在源极区域和漏极区域之间的凹陷区域。

37. 发明授权

US08451645B2 Variable resistance memory devices and methods of programming variable resistance memory devices 有权
标题翻译：可变电阻存储器件和编程可变电阻存储器件的方法
公开(公告)号：US08451645B2
公开(公告)日：2013-05-28
申请号：US12851681
申请日：2010-08-06
申请人： Hong-Sik Yoon , Min-Young Park , In-Gyu Baek , Hyun-Jun Sim , Jin-Shi Zhao
发明人： Hong-Sik Yoon , Min-Young Park , In-Gyu Baek , Hyun-Jun Sim , Jin-Shi Zhao
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C2013/0066
摘要： A variable resistance memory device includes a variable resistance memory cell, and a by-pass circuit configured to electrically by-pass a programming pulse supplied to the variable resistance memory cell after a resistive state of the variable resistance memory cell has changed in response to the programming pulse.
摘要翻译：可变电阻存储器件包括可变电阻存储器单元和旁路电路，配置为在可变电阻存储单元的电阻状态响应于可变电阻存储单元的电阻状态发生变化之后，对提供给可变电阻存储单元的编程脉冲进行电旁路编程脉冲。

38. 发明授权

US08264018B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08264018B2
公开(公告)日：2012-09-11
申请号：US12777683
申请日：2010-05-11
申请人： Hong Sik Yoon , Jinshi Zhao , Ingyu Baek , Hyun Jun Sim , Minyoung Park
发明人： Hong Sik Yoon , Jinshi Zhao , Ingyu Baek , Hyun Jun Sim , Minyoung Park
IPC分类号： H01L29/80
CPC分类号： H01L27/228 , H01L27/0207 , H01L27/2454 , H01L27/249
摘要： Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.
摘要翻译：提供了一种半导体存储器件。半导体存储器件可以包括在基本上垂直于半导体衬底的上表面的方向上延伸的局部位线和与局部位线相交的局部字线。局部位线电连接到贯穿位线晶体管的栅极的位线通道柱，并且本地字线电连接到贯穿字线晶体管的栅极的字线通道柱。

39. 发明授权

US08007875B2 Method of forming a carbon nano-tube 有权
标题翻译：形成碳纳米管的方法
公开(公告)号：US08007875B2
公开(公告)日：2011-08-30
申请号：US11832601
申请日：2007-08-01
申请人： Hong-Sik Yoon , Young-Moon Choi , Sun-Woo Lee
发明人： Hong-Sik Yoon , Young-Moon Choi , Sun-Woo Lee
IPC分类号： H05H1/24
CPC分类号： B82Y40/00 , B82Y30/00 , C01B32/162 , Y10S977/742
摘要： In a method of forming carbon nano-tubes, a catalytic film is formed on a substrate. The catalytic film is then transformed into preliminary catalytic particles. Thereafter, the preliminary catalytic particles are transformed into catalytic particles. Carbon nano-tubes then grow from the catalytic particles. The carbon nano-tubes have relatively high conductivity and high number density.
摘要翻译：在形成碳纳米管的方法中，在基板上形成催化膜。然后将催化膜转化成预催化颗粒。此后，将预催化剂颗粒转化成催化剂颗粒。碳纳米管然后从催化颗粒生长。碳纳米管具有较高的导电性和高密度。

40. 发明申请

US20110032747A1 VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF PROGRAMMING VARIABLE RESISTANCE MEMORY DEVICES 有权
标题翻译：可变电阻记忆体装置和编程可变电阻记忆装置的方法
公开(公告)号：US20110032747A1
公开(公告)日：2011-02-10
申请号：US12851681
申请日：2010-08-06
申请人： Hong-Sik Yoon , Min-Young Park , In-Gyu Baek , Hyun-Jun Sim , Jin-Shi Zhao
发明人： Hong-Sik Yoon , Min-Young Park , In-Gyu Baek , Hyun-Jun Sim , Jin-Shi Zhao
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C2013/0066
摘要： A variable resistance memory device includes a variable resistance memory cell, and a by-pass circuit configured to electrically by-pass a programming pulse supplied to the variable resistance memory cell after a resistive state of the variable resistance memory cell has changed in response to the programming pulse.
摘要翻译：可变电阻存储器件包括可变电阻存储器单元和旁路电路，配置为在可变电阻存储单元的电阻状态响应于可变电阻存储单元的电阻状态发生变化之后，对提供给可变电阻存储单元的编程脉冲进行电旁路编程脉冲。

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