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31. 发明申请

US20100055831A1 PHASE CHANGEABLE MEMORY CELL ARRAY REGION AND METHOD OF FORMING THE SAME 有权
标题翻译：相变记忆体区域及其形成方法
公开(公告)号：US20100055831A1
公开(公告)日：2010-03-04
申请号：US12617782
申请日：2009-11-13
申请人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
发明人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
IPC分类号： H01L21/06
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/165 , H01L45/1666
摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.
摘要翻译：相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。该区域还包括穿过下层间绝缘层设置的多个导电插塞。所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

32. 发明授权

US07638788B2 Phase change memory device and method of forming the same 有权
标题翻译：相变存储器件及其形成方法
公开(公告)号：US07638788B2
公开(公告)日：2009-12-29
申请号：US11974774
申请日：2007-10-16
申请人： Dong-Ho Ahn , Hideki Horii , Jong-Chan Shin , Jun-Soo Bae , Hyeong-Geun An
发明人： Dong-Ho Ahn , Hideki Horii , Jong-Chan Shin , Jun-Soo Bae , Hyeong-Geun An
IPC分类号： H01L29/04
CPC分类号： H01L45/143 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1226 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： Provided are a phase change memory device and a method of forming the same. According to the phase change memory, a first plug electrode and a second plug electrode are spaced apart from each other in a mold insulating layer. A phase change pattern is disposed on the mold insulating layer. The phase change pattern contacts a top of the first plug electrode and a first potion of a top of the second plug electrode. An interconnection is electrically connected to a second portion of the top of the second plug electrode.
摘要翻译：提供了一种相变存储器件及其形成方法。根据相变存储器，第一插头电极和第二插头电极在模具绝缘层中彼此间隔开。相变图案设置在模具绝缘层上。相变图案接触第一插头电极的顶部和第二插头电极的顶部的第一部分。互连电连接到第二插头电极的顶部的第二部分。

33. 发明授权

US07605087B2 Methods of forming semiconductor devices using di-block polymer layers 有权
标题翻译：使用二嵌段聚合物层形成半导体器件的方法
公开(公告)号：US07605087B2
公开(公告)日：2009-10-20
申请号：US11830284
申请日：2007-07-30
申请人： Hideki Horii
发明人： Hideki Horii
IPC分类号： H01L21/311
CPC分类号： H01L45/06 , H01L21/31144 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： A method of forming a semiconductor device is provided. An interlayer dielectric is formed on a substrate. A di-block polymer layer that includes a plurality of first polymer blocks and a plurality of second polymer blocks is formed on the interlayer dielectric. The di-block polymer layer is divided into a first phase to which the first polymer blocks are bound and a second phase to which the second polymer blocks are bound. The second phase is removed so that at least part of the first phase remains in place, where the remaining first phase defines at least part of a pore. The interlayer dielectric that is exposed beneath the pore is etched to form an opening. The opening may have a smaller width than the minimum feature size that a photolithography process is capable of resolving. As a result, a linewidth of an electrode that may be formed to fill the opening may be reduced.
摘要翻译：提供一种形成半导体器件的方法。在基板上形成层间电介质。在层间电介质上形成包含多个第一聚合物嵌段和多个第二聚合物嵌段的二嵌段聚合物层。二嵌段聚合物层被分成与第一聚合物嵌段结合的第一相和第二聚合物嵌段结合的第二相。去除第二相，使得第一相的至少一部分保持在适当位置，其中剩余的第一相定义至少一部分孔。蚀刻在孔下方露出的层间电介质以形成开口。开口可以具有比光刻工艺能够分辨的最小特征尺寸更小的宽度。结果，可以减少可形成为填充开口的电极的线宽。

34. 发明授权

US07569430B2 Phase changeable structure and method of forming the same 有权
标题翻译：相变结构及其形成方法
公开(公告)号：US07569430B2
公开(公告)日：2009-08-04
申请号：US11674580
申请日：2007-02-13
申请人： Jun-Soo Bae , Hideki Horii , Ji-Hye Yi , Young-Soo Lim
发明人： Jun-Soo Bae , Hideki Horii , Ji-Hye Yi , Young-Soo Lim
IPC分类号： H01L21/82
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： The present invention relates to a phase changeable structure having decreased amounts of defects and a method of forming the phase changeable structure. A stacked composite is first formed by (i) forming a phase changeable layer including a chalcogenide is formed on a lower electrode, (ii) forming an etch stop layer having a first etch rate with respect to a first etching material including chlorine on the phase changeable layer, and (iii) forming a conductive layer having a second etch rate with respect to the first etching material on the etch stop layer. The conductive layer of the stacked composite is then etched using the first etching material to form an upper electrode. The etch stop layer and the phase changeable layer are then etched using a second etching material that is substantially flee of chlorine to form an etch stop pattern and a phase changeable pattern, respectively.
摘要翻译：本发明涉及具有减少的缺陷量的相变结构和形成相变结构的方法。首先通过（i）在下电极上形成包括硫族化物的相变层来形成堆叠复合体，（ii）形成相对于在相上包括氯的第一蚀刻材料具有第一蚀刻速率的蚀刻停止层可变层，和（iii）形成相对于蚀刻停止层上的第一蚀刻材料具有第二蚀刻速率的导电层。然后使用第一蚀刻材料蚀刻层叠复合体的导电层以形成上电极。然后使用基本上不含氯的第二蚀刻材料来蚀刻蚀刻停止层和相变层，以分别形成蚀刻停止图案和相变图案。

35. 发明申请

US20080237566A1 Phase change memory device and method of fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20080237566A1
公开(公告)日：2008-10-02
申请号：US11905244
申请日：2007-09-28
申请人： Hyeong-Geun AN , Hideki HORII , Jong-Chan SHIN , Dong-Ho AHN , Jun-Soo BAE , Jeong-Hee PARK
发明人： Hyeong-Geun AN , Hideki HORII , Jong-Chan SHIN , Dong-Ho AHN , Jun-Soo BAE , Jeong-Hee PARK
IPC分类号： H01L47/00
CPC分类号： H01L27/2463 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1683
摘要： A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode. Upper surfaces of the first and second phase change patterns may be on the same plane
摘要翻译：提供了一种相变存储器件及其制造方法。具有第一表面的第一电极设置在基板上。具有与第一表面不同的第二表面的第二电极在基板上。第二电极可以与第一电极间隔开。可以对应于第一电极形成第三电极。可以对应于第二电极形成第四电极。可以在第一表面和第三电极之间插入第一相变图案。可以在第二表面和第四电极之间插入第二相变图案。第一和第二相变图案的上表面可以在同一平面上

36. 发明申请

US20080149910A1 PHASE-CHANGE MEMORY DEVICE HAVING PHASE CHANGE MATERIAL PATTERN SHARED BETWEEN ADJACENT CELLS AND ELECTRONIC PRODUCT INCLUDING THE PHASE-CHANGE MEMORY 有权
标题翻译：具有相变细胞之间的相变材料相位变化的相变存储器件和包括相变存储器的电子产品
公开(公告)号：US20080149910A1
公开(公告)日：2008-06-26
申请号：US11941173
申请日：2007-11-16
申请人： Hyeong-geun AN , Hideki HORII , Jong-chan SHIN , Dong-ho AHN , Jun-soo BAE
发明人： Hyeong-geun AN , Hideki HORII , Jong-chan SHIN , Dong-ho AHN , Jun-soo BAE
IPC分类号： H01L47/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Provided is a phase-change memory device including a phase-change material pattern of which strips are shared by neighboring cells. The phase-change memory device includes a plurality of bottom electrodes arranged in a matrix array. The phase-change material pattern is formed on the bottom electrodes, and the strips of the phase-change material pattern are electrically connected to the bottom electrodes. Each strip of the phase-change material pattern is connected to at least two diagonally neighboring bottom electrodes of the bottom electrodes.
摘要翻译：提供了一种相变存储器件，其包括相邻单元共享条带的相变材料图案。相变存储器件包括以矩阵阵列排列的多个底部电极。相变材料图案形成在底部电极上，相变材料图案的条带电连接到底部电极。相变材料图案的每个条带连接到底部电极的至少两个对角相邻的底部电极。

37. 发明申请

US20080048293A1 SEMICONDUCTOR DEVICE HAVING HEATING STRUCTURE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：具有加热结构的半导体器件及其形成方法
公开(公告)号：US20080048293A1
公开(公告)日：2008-02-28
申请号：US11842183
申请日：2007-08-21
申请人： Hideki Horii
发明人： Hideki Horii
IPC分类号： H01L47/00 , H01L21/8234 , H01L29/00 , H01L21/20
CPC分类号： H01L27/2463 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/16
摘要： A semiconductor device includes a lower electrode including a bottom wall portion and a sidewall portion extending upwardly from the bottom wall portion, and an insulating layer located over a top edge surface of the sidewall portion of the lower electrode. The insulating layer includes a contact window which partially exposes the top edge surface of the sidewall portion of the lower electrode. The device further includes a heated pattern which contacts the partially exposed top edge surface of the sidewall portion of the lower electrode through the contact window of the insulating layer.
摘要翻译：半导体器件包括下电极，其包括底壁部分和从底壁部分向上延伸的侧壁部分，以及位于下电极的侧壁部分的顶部边缘表面上方的绝缘层。绝缘层包括部分地暴露下电极的侧壁部分的顶边缘表面的接触窗口。该装置还包括加热图案，其通过绝缘层的接触窗接触下部电极的侧壁部分的部分露出的顶部边缘表面。

38. 发明授权

US07038261B2 Integrated circuit memory devices having memory cells therein that utilize phase-change materials to support non-volatile data retention 有权
标题翻译：其中具有存储单元的集成电路存储器件利用相变材料来支持非易失性数据保持
公开(公告)号：US07038261B2
公开(公告)日：2006-05-02
申请号：US10421320
申请日：2003-04-23
申请人： Hideki Horii
发明人： Hideki Horii
IPC分类号： H01L29/76
CPC分类号： H01L29/685 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： An integrated circuit memory device includes a semiconductor substrate and a first electrically insulating layer that extends on the semiconductor substrate and has a first contact hole extending therethrough. An electrically conductive plug is provided in the first contact hole. A phase-change material layer pattern is provided as a non-volatile storage medium. The phase-change material layer pattern has a bottom surface that is electrically connected to the electrically conductive plug. A second electrically insulating layer is provided on the phase-change material layer pattern. The second electrically insulating layer has a second contact hole therein. This contact hole exposes a portion of an upper surface of the phase-change material layer pattern. To improve data writing efficiency, the area of the exposed portion of the upper surface of the phase-change material layer pattern is less than a maximum cross-sectional area of the electrically conductive plug. A plate electrode is also provided. This plate electrode is electrically connected to the phase-change material layer pattern. Barrier layers may also be provided directly on the plug and directly on the exposed portion of the upper surface.
摘要翻译：集成电路存储器件包括半导体衬底和第一电绝缘层，其在半导体衬底上延伸并且具有延伸穿过其中的第一接触孔。导电插头设置在第一接触孔中。提供相变材料层图案作为非挥发性存储介质。相变材料层图案具有电连接到导电插塞的底表面。在相变材料层图案上设置第二电绝缘层。第二电绝缘层中具有第二接触孔。该接触孔露出相变材料层图案的上表面的一部分。为了提高数据写入效率，相变材料层图案的上表面的露出部分的面积小于导电插塞的最大横截面面积。还提供了平板电极。该平板电极与相变材料层图案电连接。阻挡层也可以直接设置在塞子上并直接设置在上表面的暴露部分上。

39. 发明授权

US07037749B2 Methods for forming phase changeable memory devices 有权
标题翻译：用于形成相变存储器件的方法
公开(公告)号：US07037749B2
公开(公告)日：2006-05-02
申请号：US10780246
申请日：2004-02-18
申请人： Hideki Horii , Suk-Ho Joo , Ji-Hye Yi
发明人： Hideki Horii , Suk-Ho Joo , Ji-Hye Yi
IPC分类号： H01L21/00 , H01L51/40
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/143 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.
摘要翻译：可相变存储器件可以包括衬底，衬底上的绝缘层，第一和第二电极以及第一和第二电极之间的相变材料的图案。更具体地，绝缘层可以在其中具有孔，并且第一电极可以在绝缘层中的孔中。此外，第二电极的部分可以延伸超过相变材料图案的边缘。还讨论了相关方法。

40. 发明授权

US06596149B2 Manufacturing method for capacitor having electrode formed by electroplating 失效
标题翻译：具有通过电镀形成电极的电容器的制造方法
公开(公告)号：US06596149B2
公开(公告)日：2003-07-22
申请号：US09323600
申请日：1999-06-01
申请人： Hideki Horii
发明人： Hideki Horii
IPC分类号： C25D502
CPC分类号： H01L28/65 , C25D3/50 , H01L21/2885
摘要： A capacitor having an electrode formed by electroplating, and a manufacturing method thereof are disclosed. According to an embodiment of the invention, a conductive film is formed on a conductive plug connected to an active region of a semiconductor substrate, and on an interlayer dielectric (ILD) film formed around the conductive plug. Then, a non-conductive pattern exposing a part of the conductive film on the conductive plug is formed on the conductive film, and a lower electrode, which is formed of a platinum (Pt) group metal, is formed on the conductive film by electroplating. In addition, the lower electrode can have a rectangular, T-shaped, reverse trapezoid or barrel-shaped cross-section. Electroplating can similarly form an upper electrode of the capacitor.
摘要翻译：公开了一种具有通过电镀形成的电极的电容器及其制造方法。根据本发明的实施例，导电膜形成在与半导体衬底的有源区连接的导电插塞上，以及形成在导电插塞周围的层间绝缘膜（ILD）膜上。然后，在导电膜上形成露出导电性膜的导电膜的一部分的非导电图案，并且通过电镀在导电膜上形成由铂（Pt）族金属形成的下电极。此外，下电极可以具有矩形，T形，倒梯形或桶形横截面。电镀可类似地形成电容器的上电极。

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