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31. 发明授权

US07221028B2 High voltage transistor and method of manufacturing the same 失效
标题翻译：高压晶体管及其制造方法
公开(公告)号：US07221028B2
公开(公告)日：2007-05-22
申请号：US10899371
申请日：2004-07-26
申请人： Tae-kwang Yu , Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
发明人： Tae-kwang Yu , Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
IPC分类号： H01L29/72
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/7835
摘要： The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.
摘要翻译：本发明涉及高压晶体管及其制造方法。高压晶体管包括：形成在半导体衬底中的沟道区; 形成在半导体衬底的沟道区上的栅极绝缘膜; 低浓度源极区和低浓度漏极区，其间具有沟道区，并且各自形成在半导体衬底中; 高浓度源区，其形成为与沟道区隔开第一距离; 高浓度漏区，其形成为与沟道区隔开距离大于第一距离的第二距离; 栅极电极，其具有与沟道区域上的栅极绝缘膜接合的栅极底部，以及与栅极底部一体化并且从栅极底部的顶部突出预定长度的栅极顶部，以在低于浓度排水区; 形成在高浓度源区上的第一金属硅化物层; 以及形成在高浓度漏极区上的第二金属硅化物层。

32. 发明申请

US20060170028A1 Non-volatile memory device, methods of fabricating and operating the same 失效
标题翻译：非易失性存储器件，其制造和操作方法
公开(公告)号：US20060170028A1
公开(公告)日：2006-08-03
申请号：US11323355
申请日：2005-12-30
申请人： Hee-Seog Jeon , Seung-Beom Yoon , Jeong-Uk Han , Yong-Tae Kim
发明人： Hee-Seog Jeon , Seung-Beom Yoon , Jeong-Uk Han , Yong-Tae Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115 , H01L27/11524 , H01L29/42328
摘要： A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.
摘要翻译：非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极通过隧道绝缘层引起电荷隧穿。选择栅电极与控制栅电极绝缘。根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。

33. 发明申请

US20060063333A1 Method of manufacturing split gate type nonvolatile memory device 失效
标题翻译：分闸式非易失性存储装置的制造方法
公开(公告)号：US20060063333A1
公开(公告)日：2006-03-23
申请号：US11262767
申请日：2005-11-01
申请人： Hee-seog Jeon , Seung-beom Yoon
发明人： Hee-seog Jeon , Seung-beom Yoon
IPC分类号： H01L21/336
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11521
摘要： A method of manufacturing a split gate type nonvolatile semiconductor memory device in which control gates are formed by a self aligning process.
摘要翻译：一种制造其中通过自对准工艺形成控制栅极的分离栅型非易失性半导体存储器件的方法。

34. 发明授权

US07015541B2 Memory cell including stacked gate sidewall patterns and method for fabricating same 有权
标题翻译：包括堆叠栅极侧壁图案的存储单元及其制造方法
公开(公告)号：US07015541B2
公开(公告)日：2006-03-21
申请号：US10758523
申请日：2004-01-14
申请人： Jae-Hwang Kim , Hee-Seog Jeon
发明人： Jae-Hwang Kim , Hee-Seog Jeon
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/66833 , H01L29/7923
摘要： A memory cell and a method for fabricating same. The memory cell comprises a source region and a drain region formed in a semiconductor substrate and a channel region defined between the source and drain regions. Charge storage layers are formed the channel region. A gate insulating layer is formed on the channel region between the charge storage layers, and a gate electrode is formed on the gate insulating layer and the charge trapping storage layers.
摘要翻译：一种存储单元及其制造方法。存储单元包括形成在半导体衬底中的源极区域和漏极区域以及限定在源极和漏极区域之间的沟道区域。电荷存储层形成沟道区。在电荷存储层之间的沟道区域上形成栅极绝缘层，并且在栅极绝缘层和电荷俘获存储层上形成栅电极。

35. 发明申请

US20050029574A1 Self-aligned 1 bit local SONOS memory cell and method of fabricating the same 失效
标题翻译：自对准1位本地SONOS存储单元及其制造方法
公开(公告)号：US20050029574A1
公开(公告)日：2005-02-10
申请号：US10912046
申请日：2004-08-06
申请人： Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
发明人： Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/112 , H01L27/115 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115
摘要： A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.
摘要翻译：自对准1比特氧化硅氮氧化物硅（SONOS）单元及其制造方法在相邻SONOS单元之间具有高均匀性，因为当蚀刻1比特的字线时，氮化物层的长度不会由于未对准而变化 SONOS细胞。在半导体衬底上形成形成字线侧壁的绝缘层图案，在其侧壁上形成用于栅极的字线。使用自对准蚀刻间隔物蚀刻ONO层提供均匀的相邻SONOS电池。

36. 发明授权

US6048773A Methods of forming bipolar junction transistors having preferred base electrode extensions and transistors formed thereby 失效
标题翻译：形成具有优选的基极延伸的双极结型晶体管和由此形成的晶体管的方法
公开(公告)号：US6048773A
公开(公告)日：2000-04-11
申请号：US85777
申请日：1998-05-28
申请人： Hee-Seog Jeon
发明人： Hee-Seog Jeon
IPC分类号： H01L29/73 , H01L21/331 , H01L29/423 , H01L29/70 , H01L29/732
CPC分类号： H01L29/66272 , H01L29/42304
摘要： Methods of forming bipolar junction transistors having preferred base electrode extensions include the steps of forming a base electrode of second conductivity type (e.g., P-type) on a face of a substrate. A conductive base electrode extension layer is then formed in contact with a sidewall of the base electrode. The base electrode extension layer may be doped or undoped. An electrically insulating base electrode spacer is then formed on the conductive base electrode extension layer, opposite the sidewall of the base electrode. The conductive base electrode extension layer is then etched to define a L-shaped base electrode extension, using the base electrode spacer as an etching mask. Dopants of second conductivity type are then diffused from the base electrode, through the base electrode extension and into the substrate to define an extrinsic base region therein. This diffusion step can be performed in a carefully controlled manner to limit the extent to which the extrinsic base region dopants adversely effect the electrical characteristics of surrounding regions or contribute to parasitic capacitance. Dopants of second conductivity type are also preferably implanted into the substrate to define an intrinsic base region therein. This dopant implant step is preferably performed using the base electrode spacer as an implant mask. Accordingly, the base electrode spacer is used advantageously as an etching mask and as a dopant implantation mask. An emitter region of first conductivity type is also preferably formed in the intrinsic base region.
摘要翻译：形成具有优选的基极延伸部的双极结型晶体管的方法包括以下步骤：在衬底的表面上形成第二导电类型的基极（例如P型）。然后形成与基极的侧壁接触的导电基极延伸层。基极延伸层可以是掺杂的或未掺杂的。然后，在与基极的侧壁相对的导电基极延伸层上形成电绝缘基极间隔物。然后，使用基极间隔件作为蚀刻掩模，蚀刻导电基极延伸层以限定L形基极延伸。然后，第二导电类型的掺杂剂从基极通过基极延伸扩散到衬底中以在其中限定非本征基区。该扩散步骤可以以仔细控制的方式进行，以限制外部碱性区域掺杂对其周围区域的电特性的不利影响或有助于寄生电容的程度。也优选将第二导电类型的掺杂剂注入到衬底中以在其中限定其内部基极区域。该掺杂剂注入步骤优选使用基极间隔物作为植入掩模进行。因此，基极隔离器有利地用作蚀刻掩模和掺杂剂注入掩模。也优选在本征基区形成第一导电类型的发射极区域。

37. 发明授权

US5747374A Methods of fabricating bipolar transistors having separately formed intrinsic base and link-up regions 失效
标题翻译：制造具有单独形成的本征基极和连接区域的双极晶体管的方法
公开(公告)号：US5747374A
公开(公告)日：1998-05-05
申请号：US757802
申请日：1996-11-27
申请人： Hee-Seog Jeon
发明人： Hee-Seog Jeon
IPC分类号： H01L29/73 , H01L21/328 , H01L21/331 , H01L29/732
CPC分类号： H01L29/66272
摘要： Methods which provide for the formation of the intrinsic base regions and the link-up regions in separate processing steps are provided. These methods include the steps of forming a first conductive layer on a substrate of a first conductivity type containing a region of a second conductivity type therein, wherein the first conductive layer is formed on the region of second conductivity type semiconductor material. The first conductive layer is patterned to define a sidewall of a window which exposes a portion of the region of a second conductivity type semiconductor material. An insulating layer is formed on the sidewall, the first conductive layer and the exposed portion of the region of second conductivity type semiconductor material. A first mask is then formed on the insulating layer which exposes a region of the insulating layer corresponding to a link-up region of the bipolar transistor. A first impurity ion of a first conductivity type is then implanted through the insulating layer using the first mask to form a link-up region. The first mask may be removed and a sidewall spacer formed on the sidewall. The insulating layer is then removed to expose a region of second conductivity type semiconductor material adjacent the sidewall spacer to define an implantation region for an intrinsic base region. A second impurity ion of the first conductivity type is then implanted in the region of second conductivity type semiconductor material using the sidewall spacer as a mask to form an intrinsic base region. Thus, an intrinsic base region and a link-up region are formed separately.
摘要翻译：提供了在单独的处理步骤中提供形成本征基区和连接区的方法。这些方法包括在其中包含第二导电类型的区域的第一导电类型的衬底上形成第一导电层的步骤，其中第一导电层形成在第二导电类型半导体材料的区域上。图案化第一导电层以限定暴露第二导电类型半导体材料区域的一部分的窗口的侧壁。绝缘层形成在第二导电型半导体材料的侧壁，第一导电层和暴露部分的侧壁上。然后在绝缘层上形成第一掩模，其暴露与双极晶体管的连接区域对应的绝缘层的区域。然后通过第一掩模通过绝缘层注入第一导电类型的第一杂质离子以形成连接区域。可以去除第一掩模并且在侧壁上形成侧壁间隔物。然后去除绝缘层以暴露与侧壁间隔物相邻的第二导电类型半导体材料的区域，以限定本征基区的注入区。然后使用侧壁间隔物作为掩模将第一导电类型的第二杂质离子注入第二导电类型半导体材料的区域中以形成本征基区。因此，分别形成本征基区和连接区。

38. 发明授权

US09318181B2 Magnetic memory devices including shared lines 有权
标题翻译：包括共享线路的磁存储器件
公开(公告)号：US09318181B2
公开(公告)日：2016-04-19
申请号：US14448717
申请日：2014-07-31
申请人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Kee-Moon Chun , Hee-Seog Jeon
发明人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Kee-Moon Chun , Hee-Seog Jeon
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1659
摘要： A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.
摘要翻译：磁存储装置包括字线，与字线交叉的位线，设置在字线和位线之间的交叉处的磁存储元件，以及连接到字线的选择晶体管。磁存储元件在多个字线之间共享字线，并且共享连接到在选择晶体管之间共享的字线的选择晶体管。还描述了相关系统和操作方法。

39. 发明申请

US20150179244A1 Magnetic Memory Devices Including Magnetic Memory Cells Having Opposite Magnetization Directions 有权
标题翻译：包括具有相反磁化方向的磁记忆体的磁存储器件
公开(公告)号：US20150179244A1
公开(公告)日：2015-06-25
申请号：US14509756
申请日：2014-10-08
申请人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Hee-Seog Jeon
发明人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Hee-Seog Jeon
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.
摘要翻译：磁存储器件包括分别耦合到第一和第二位线的第一和第二磁存储器单元。第一和第二磁存储单元分别包括钉扎磁性层，自由磁性层和隧道绝缘层。固定磁性层，隧道绝缘层和自由磁性层的各个堆叠顺序在第一和第二磁性存储单元中是不同的。磁存储器件还包括至少一个晶体管，其被配置为将第一和第二磁存储器单元耦合到公共源极线。还讨论了相关的操作方法。

40. 发明授权

US07944753B2 Electrically erasable programmable read-only memory (EEPROM) cell and methods for forming and reading the same 有权
标题翻译：电可擦除可编程只读存储器（EEPROM）单元及其形成和读取方法
公开(公告)号：US07944753B2
公开(公告)日：2011-05-17
申请号：US12912517
申请日：2010-10-26
申请人： Yong-Kyu Lee , Jeong-Uk Han , Hee-Seog Jeon , Jung-Ho Moon , Soung-Youb Ha
发明人： Yong-Kyu Lee , Jeong-Uk Han , Hee-Seog Jeon , Jung-Ho Moon , Soung-Youb Ha
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C16/26 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.
摘要翻译：在EEPROM单元中读取数据的方法中，用于读取的位线电压被施加到包括存储晶体管和选择晶体管的EEPROM单元。第一电压被施加到存储晶体管的感测线。大于第一电压的第二电压被施加到选择晶体管的字线。将通过EEPROM单元的电流与预定的参考电流进行比较，以读取存储在EEPROM单元中的数据。可以在擦除状态下增加EEPROM单元的通电池电流，并且可以容易地区分单元中的数据。

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