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1. 发明申请

US20050035404A1 High voltage transistor and method of manufacturing the same 失效
标题翻译：高压晶体管及其制造方法
公开(公告)号：US20050035404A1
公开(公告)日：2005-02-17
申请号：US10899371
申请日：2004-07-26
申请人： Tae-kwang Yu , Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
发明人： Tae-kwang Yu , Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
IPC分类号： H01L29/41 , H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/788 , H01L29/792 , H01L31/0328
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/7835
摘要： The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.
摘要翻译：本发明涉及高压晶体管及其制造方法。高压晶体管包括：形成在半导体衬底中的沟道区; 形成在半导体衬底的沟道区上的栅极绝缘膜; 低浓度源极区和低浓度漏极区，其间具有沟道区，并且各自形成在半导体衬底中; 高浓度源区，其形成为与沟道区隔开第一距离; 高浓度漏区，其形成为与沟道区隔开距离大于第一距离的第二距离; 栅极电极，其具有与沟道区域上的栅极绝缘膜接合的栅极底部，以及与栅极底部一体化并且从栅极底部的顶部突出预定长度的栅极顶部，以在低于浓度排水区; 形成在高浓度源区上的第一金属硅化物层; 以及形成在高浓度漏极区上的第二金属硅化物层。

2. 发明授权

US07422949B2 High voltage transistor and method of manufacturing the same 失效
标题翻译：高压晶体管及其制造方法
公开(公告)号：US07422949B2
公开(公告)日：2008-09-09
申请号：US11732765
申请日：2007-04-04
申请人： Tae-kwang Yu , Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
发明人： Tae-kwang Yu , Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
IPC分类号： H01L29/72
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/7835
摘要： The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.
摘要翻译：本发明涉及高压晶体管及其制造方法。高压晶体管包括：形成在半导体衬底中的沟道区; 形成在半导体衬底的沟道区上的栅极绝缘膜; 低浓度源极区和低浓度漏极区，其间具有沟道区，并且各自形成在半导体衬底中; 高浓度源区，其形成为与沟道区隔开第一距离; 高浓度漏区，其形成为与沟道区隔开距离大于第一距离的第二距离; 栅极电极，其具有与沟道区域上的栅极绝缘膜接合的栅极底部，以及与栅极底部一体化并且从栅极底部的顶部突出预定长度的栅极顶部，以在低于浓度排水区; 形成在高浓度源区上的第一金属硅化物层; 以及形成在高浓度漏极区上的第二金属硅化物层。

3. 发明申请

US20070184622A1 High voltage transistor and method of manufacturing the same 失效
公开(公告)号：US20070184622A1
公开(公告)日：2007-08-09
申请号：US11732765
申请日：2007-04-04
申请人： Tae-kwang Yu , Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
发明人： Tae-kwang Yu , Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/7835
摘要： The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.

4. 发明授权

US07221028B2 High voltage transistor and method of manufacturing the same 失效
标题翻译：高压晶体管及其制造方法
公开(公告)号：US07221028B2
公开(公告)日：2007-05-22
申请号：US10899371
申请日：2004-07-26
申请人： Tae-kwang Yu , Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
发明人： Tae-kwang Yu , Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
IPC分类号： H01L29/72
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/7835
摘要： The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.
摘要翻译：本发明涉及高压晶体管及其制造方法。高压晶体管包括：形成在半导体衬底中的沟道区; 形成在半导体衬底的沟道区上的栅极绝缘膜; 低浓度源极区和低浓度漏极区，其间具有沟道区，并且各自形成在半导体衬底中; 高浓度源区，其形成为与沟道区隔开第一距离; 高浓度漏区，其形成为与沟道区隔开距离大于第一距离的第二距离; 栅极电极，其具有与沟道区域上的栅极绝缘膜接合的栅极底部，以及与栅极底部一体化并且从栅极底部的顶部突出预定长度的栅极顶部，以在低于浓度排水区; 形成在高浓度源区上的第一金属硅化物层; 以及形成在高浓度漏极区上的第二金属硅化物层。

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