专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20080116437A1 Phase Change Memory Device and Method of Forming the Same 有权
标题翻译：相变存储器件及其形成方法
公开(公告)号：US20080116437A1
公开(公告)日：2008-05-22
申请号：US11769532
申请日：2007-06-27
申请人： Gyu-Hwan Oh , In-Sun Park , Hyun-Seok Lim , Ki-Jong Lee , Nak-Hyun Lim
发明人： Gyu-Hwan Oh , In-Sun Park , Hyun-Seok Lim , Ki-Jong Lee , Nak-Hyun Lim
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A phase change memory device includes a current restrictive element interposed between an electrically conductive element and a phase change material. The current restrictive element includes a plurality of overlapping film patterns, each of which having a respective first portion proximal to the conductive element and a second portion proximal to the phase change material. The second portions are configured and dimensioned to have higher resistance than the first portions.
摘要翻译：相变存储器件包括介于导电元件和相变材料之间的电流限制元件。电流限制元件包括多个重叠的膜图案，每个重叠的膜图案具有靠近导电元件的相应的第一部分和靠近相变材料的第二部分。第二部分的构造和尺寸设计成具有比第一部分更高的电阻。

32. 发明申请

US20080032208A1 Overlay mark and method of forming the same 有权
标题翻译：叠加标记和形成方法
公开(公告)号：US20080032208A1
公开(公告)日：2008-02-07
申请号：US11826745
申请日：2007-07-18
申请人： Dae-Joung Kim , Ji-Yong You , Hyun-Seok Lim
发明人： Dae-Joung Kim , Ji-Yong You , Hyun-Seok Lim
IPC分类号： G03F1/00
CPC分类号： G03F7/70633
摘要： An overlay mark may include a main overlay pattern and an auxiliary overlay pattern, wherein the main overlay pattern may have an opening exposing a substrate and the auxiliary overlay pattern may be formed in the opening. The auxiliary overlay pattern may be spaced apart from a sidewall of the main overlay pattern defining the opening. The thickness ratio of the auxiliary overlay pattern to the main overlay pattern may be about 0.05:1 to about 0.30:1. Accordingly, overlay accuracy measurements may be improved using the clearer overlay mark according to example embodiments.
摘要翻译：覆盖标记可以包括主覆盖图案和辅助覆盖图案，其中主覆盖图案可以具有暴露基板的开口，并且可以在开口中形成辅助覆盖图案。辅助覆盖图案可以与限定开口的主覆盖图案的侧壁间隔开。辅助覆盖图案与主覆盖图案的厚度比可以为约0.05:1至约0.30:1。因此，可以使用根据示例性实施例的更清晰的覆盖标记来改善覆盖精度测量。

33. 发明申请

US20070289609A1 METHOD FOR CLEANING A PROCESS CHAMBER 审中-公开
标题翻译：清洗过程室的方法
公开(公告)号：US20070289609A1
公开(公告)日：2007-12-20
申请号：US11765356
申请日：2007-06-19
申请人： Hyun-Seok LIM , Gyu-Hwan OH , Rak-Hwan KIM , Keon-Hoe BAE , In-Sun PARK , Ki-Jong LEE
发明人： Hyun-Seok LIM , Gyu-Hwan OH , Rak-Hwan KIM , Keon-Hoe BAE , In-Sun PARK , Ki-Jong LEE
IPC分类号： B08B9/00 , B08B3/00
CPC分类号： B08B7/00 , C23C16/4405
摘要： According to an embodiment of the present invention, a method for cleaning a process chamber includes removing a TiAlN layer from an inner wall of the process chamber using a first cleaning gas containing a TiCl4 gas. According to principles of this invention, dry cleaning, without wet cleaning, is possible for cleaning the process chamber.
摘要翻译：根据本发明的一个实施例，一种用于清洁处理室的方法包括使用含有TiCl 4气体的第一清洁气体从处理室的内壁去除TiAlN层。根据本发明的原理，无需湿法清洁即可清洁处理室。

34. 发明申请

US20060110533A1 Methods and apparatus for forming a titanium nitride layer 审中-公开
标题翻译：用于形成氮化钛层的方法和装置
公开(公告)号：US20060110533A1
公开(公告)日：2006-05-25
申请号：US11281163
申请日：2005-11-17
申请人： Wan-Goo Hwang , Myeong-Jin Kim , Seung-Ki Chae , Hyun-Seok Lim , Kyoung-Ho Jang
发明人： Wan-Goo Hwang , Myeong-Jin Kim , Seung-Ki Chae , Hyun-Seok Lim , Kyoung-Ho Jang
IPC分类号： C23C16/00 , B05C11/00
CPC分类号： H01L21/67109 , C23C16/34 , C23C16/45546 , H01L21/28556 , H01L21/67757
摘要： A method of forming a titanium nitride layer by an atomic layer deposition process using a batch-type vertical reaction furnace is described wherein a first source gas including a titanium precursor is provided onto substrates loaded in a process chamber for a first time period; a first purge gas is introduced into the process chamber for a second time period shorter than the first time period; a second source gas including nitrogen is provided onto the substrates for a third time period substantially identical to the first time period; and, a second purge gas is introduced into the process chamber for a fourth time period substantially identical to the second time period. Titanium nitride layers having uniform thickness and good step coverage may thus be formed while realizing a greatly reduced manufacturing time.
摘要翻译：描述了通过使用间歇式立式反应炉的原子层沉积工艺形成氮化钛层的方法，其中包括钛前体的第一源气体在第一时间段内被装载到处理室中的基板上; 将第一吹扫气体引入处理室中比第一时间段短的第二时间段; 包括氮的第二源气体在基板上提供与第一时间段基本相同的第三时间段; 并且将第二吹扫气体与第二时间段基本相同的第四时间段引入到处理室中。因此可以在实现大大缩短的制造时间的同时形成具有均匀厚度和良好阶梯覆盖的氮化钛层。

35. 发明申请

US20050146045A1 Method for forming tungsten contact plug 有权
标题翻译：形成钨接触塞的方法
公开(公告)号：US20050146045A1
公开(公告)日：2005-07-07
申请号：US11002682
申请日：2004-12-03
申请人： Ji-Soon Park , Hyun-Seok Lim , Eung-Joon Lee , Jung-Wook Kim
发明人： Ji-Soon Park , Hyun-Seok Lim , Eung-Joon Lee , Jung-Wook Kim
IPC分类号： H01L21/28 , H01L21/285 , H01L21/44 , H01L21/768
CPC分类号： H01L21/28562 , H01L21/76843 , H01L21/76844 , H01L21/76876 , H01L21/76879 , H01L2221/1089
摘要： A method for forming a tungsten contact plug of a semiconductor device including depositing an insulating layer on a semiconductor substrate, etching the insulating layer to form a contact hole, which exposes a conductive region, forming a barrier layer on the semiconductor substrate having the contact hole, changing characteristics of a portion of the barrier layer on the insulating layer and the portion of the barrier layer in the contact hold such that the characteristics between the barrier layer on the insulating layer and the barrier layer in the contact hole differ, depositing a tungsten layer for forming the tungsten contact plug, on the barrier layer, and removing the tungsten layer from the upper portion of the insulating layer to planarize the semiconductor device.
摘要翻译：一种用于形成半导体器件的钨接触插塞的方法，包括在半导体衬底上沉积绝缘层，蚀刻绝缘层以形成接触孔，其暴露导电区域，在具有接触孔的半导体衬底上形成阻挡层改变绝缘层上的阻挡层的一部分和接触保持部中阻挡层的部分的特性，使得绝缘层上的阻挡层与接触孔中的阻挡层之间的特性不同，沉积钨在阻挡层上形成钨接触塞的层，以及从绝缘层的上部去除钨层以使半导体器件平坦化。

36. 发明授权

US06372598B1 Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same 有权
公开(公告)号：US06372598B1
公开(公告)日：2002-04-16
申请号：US09334588
申请日：1999-06-16
申请人： Sang-bum Kang , Yun-sook Chae , Sang-in Lee , Hyun-seok Lim , Mee-young Yoon
发明人： Sang-bum Kang , Yun-sook Chae , Sang-in Lee , Hyun-seok Lim , Mee-young Yoon
IPC分类号： H01L2120
摘要： A selective metal layer formation method, a capacitor formation method using the same, and a method of forming an ohmic layer on a contact hole and filling the contact hole using the same, are provided. A sacrificial metal layer is selectively deposited on a conductive layer by supplying a sacrificial metal source gas which deposits selectively on a semiconductor substrate having an insulating film and the conductive layer. Sacrificial metal atoms and a halide are formed, and the sacrificial metal layer is replaced with a deposition metal layer such as titanium Ti or platinum Pt, by supplying a metal halide gas having a halogen coherence smaller than the halogen coherence of the metal atoms in the sacrificial metal layer. If such a process is used to form a capacitor lower electrode or form an ohmic layer on the bottom of a contact hole, a metal layer can be selectively formed at a temperature of 500° C. or lower.

37. 发明授权

US10008410B2 Deposition apparatus including UV annealing unit and method for fabricating non-volatile memory device by using the deposition apparatus 有权
公开(公告)号：US10008410B2
公开(公告)日：2018-06-26
申请号：US15464532
申请日：2017-03-21
申请人： Kwang Chul Park , Ji Woon Im , Dai Hong Kim , Il Woo Kim , Hyun Seok Lim
发明人： Kwang Chul Park , Ji Woon Im , Dai Hong Kim , Il Woo Kim , Hyun Seok Lim
IPC分类号： H01L21/768 , H01L21/02 , H01L21/311 , H01L21/28 , H01L27/1157 , H01L27/11582 , C23C16/48 , C23C16/50 , C23C16/54
CPC分类号： H01L21/76825 , C23C16/45523 , C23C16/482 , C23C16/50 , C23C16/54 , C23C16/56 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02274 , H01L21/02348 , H01L21/31111 , H01L21/76802 , H01L21/76877 , H01L27/1157 , H01L27/11582 , H01L29/40117
摘要： A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.

38. 发明申请

US20180108664A1 Memory Devices Using Etching Stop Layers 有权
公开(公告)号：US20180108664A1
公开(公告)日：2018-04-19
申请号：US15604028
申请日：2017-05-24
申请人： Jeong Gil Lee , Jee Yong Kim , Jung Hwan Lee , Dae Seok Byeon , Hyun Seok Lim
发明人： Jeong Gil Lee , Jee Yong Kim , Jung Hwan Lee , Dae Seok Byeon , Hyun Seok Lim
IPC分类号： H01L27/1157 , H01L27/11524 , H01L23/535 , H01L29/06 , H01L29/788 , H01L29/792 , H01L29/423 , G11C16/10 , G11C16/26 , G11C16/08
CPC分类号： H01L27/1157 , G11C16/08 , G11C16/10 , G11C16/26 , H01L23/535 , H01L27/11524 , H01L27/11575 , H01L27/11582 , H01L29/0649 , H01L29/42328 , H01L29/42344 , H01L29/788 , H01L29/792
摘要： A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

39. 发明申请

US20110073832A1 PHASE-CHANGE MEMORY DEVICE 审中-公开
标题翻译：相变存储器件
公开(公告)号：US20110073832A1
公开(公告)日：2011-03-31
申请号：US12892419
申请日：2010-09-28
申请人： Hyun-Seok LIM , Shin-Jae Kang , Tai-Soo Lim , Jong-Cheol Lee , Jae-Hyoung Choi
发明人： Hyun-Seok LIM , Shin-Jae Kang , Tai-Soo Lim , Jong-Cheol Lee , Jae-Hyoung Choi
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/16
摘要： A phase-change memory device, including a lower electrode, a phase-change material pattern electrically connected to the lower electrode, and an upper electrode electrically connected to the phase-change material pattern. The lower electrode may include a first structure including a metal semiconductor compound, a second structure on the first structure, the second structure including a metal nitride material, and including a lower part having a greater width than an upper part, and a third structure including a metal nitride material containing an element X, the third structure being on the second structure, the element X including at least one selected from the group of silicon, boron, aluminum, oxygen, and carbon.
摘要翻译：相变存储器件，包括下电极，电连接到下电极的相变材料图案，以及电连接到相变材料图案的上电极。下电极可以包括第一结构，其包括金属半导体化合物，第一结构上的第二结构，第二结构包括金属氮化物材料，并且包括具有比上部宽度更大的下部的第一结构，以及包括包含元素X的金属氮化物材料，第三结构在第二结构上，元素X包括选自硅，硼，铝，氧和碳中的至少一种。

40. 发明授权

US07719045B2 Capacitor for a semiconductor device and method of forming the same 有权
标题翻译：用于半导体器件的电容器及其形成方法
公开(公告)号：US07719045B2
公开(公告)日：2010-05-18
申请号：US12251352
申请日：2008-10-14
申请人： Young-Joo Cho , Hyun-Seok Lim , Rak-Hwan Kim , Jung-Wook Kim , Hyun-Suk Lee
发明人： Young-Joo Cho , Hyun-Seok Lim , Rak-Hwan Kim , Jung-Wook Kim , Hyun-Suk Lee
IPC分类号： H01L27/108
CPC分类号： H01L28/90 , H01L27/0207 , H01L27/10852 , H01L28/75
摘要： In a capacitor having a high dielectric constant, the capacitor includes a cylindrical lower electrode, a dielectric layer and an upper electrode. A metal oxide layer is formed on inner, top and outer surfaces of the lower electrode as the dielectric layer. A first sub-electrode is formed on a surface of the dielectric layer along the profile of the lower electrode and a second sub-electrode is continuously formed on the first sub-electrode corresponding to the top surface of the lower electrode, so an opening portion of the lower electrode is covered with the second sub-electrode. The first and second sub-electrodes include first and second metal nitride layers in which first and second stresses are applied, respectively. Directions of the first and second stresses are opposite to each other. Accordingly, cracking is minimized in the upper electrode with the high dielectric constant, thereby reducing current leakage.
摘要翻译：在具有高介电常数的电容器中，电容器包括圆柱形下电极，电介质层和上电极。在作为电介质层的下电极的内表面，顶面和外表面上形成金属氧化物层。第一子电极沿着下电极的轮廓在电介质层的表面上形成，并且第二子电极连续形成在与下电极的顶表面对应的第一子电极上，因此开口部分的下部电极被第二子电极覆盖。第一和第二子电极分别包括施加第一和第二应力的第一和第二金属氮化物层。第一和第二个应力的方向彼此相反。因此，在具有高介电常数的上电极中破裂最小化，从而减少电流泄漏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式