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31. 发明申请

US20140184435A1 Successive Approximation Register Analog-to-Digital Converter with Multiple Capacitive Sampling Circuits and Method 有权
标题翻译：具有多个电容采样电路的连续近似寄存器模数转换器和方法
公开(公告)号：US20140184435A1
公开(公告)日：2014-07-03
申请号：US13732113
申请日：2012-12-31
申请人： Xiaodong Wang , Shouli Yan , Axel Thomsen , Jinwen Xiao
发明人： Xiaodong Wang , Shouli Yan , Axel Thomsen , Jinwen Xiao
IPC分类号： H03M1/38 , H03K5/24
CPC分类号： H03M1/38 , H03K5/24 , H03M1/00 , H03M1/0695 , H03M1/12 , H03M1/1225 , H03M1/1245 , H03M1/466 , H03M1/804
摘要： A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.
摘要翻译：电路包括比较器，其包括第一输入端，第二输入端和输出端。电路还包括被配置为选择性地耦合到第一和第二输入的多个电容性采样电路。多个电容性采样电路中的每一个包括第一和第二电容器，并且包括被配置为分别将第一和第二电容器选择性地耦合到第一和第二输入端的第一和第二转换开关。多个电容性采样电路中的所选择的一个电容性采样电路的第一和第二转换开关闭合，以在转换阶段将所选择的一个耦合到比较器的第一和第二输入端。

32. 发明申请

US20140184331A1 Amplifier Circuits and Methods of Amplifying an Input Signal 有权
标题翻译：放大器电路和放大输入信号的方法
公开(公告)号：US20140184331A1
公开(公告)日：2014-07-03
申请号：US13732135
申请日：2012-12-31
申请人： Axel Thomsen , Gang Yuan
发明人： Axel Thomsen , Gang Yuan
IPC分类号： H03F3/45
CPC分类号： H03F3/005 , H03F3/45197 , H03F3/45645 , H03F2203/45404 , H03F2203/45418 , H03F2203/45421 , H03F2203/45424 , H03F2203/45444 , H03F2203/45446 , H03F2203/45528 , H03F2203/45648
摘要： A method of operating an amplifier circuit having a pre-charge phase and a sample/conversion phase includes, during a pre-charge phase, charging first and second capacitors to first and second bias voltages. The first capacitor is coupled to a first input of an amplifier circuit, which has a second input and an output. The second capacitor is coupled to the second input. During a sample/conversion phase, the first input of the amplifier circuit is coupled to an input signal through the first capacitor to level-shift the input signal according to the first bias voltage and the output of the amplifier is coupled to the second input through the second capacitor to level shift a feedback signal according to the second bias voltage.
摘要翻译：操作具有预充电阶段和采样/转换阶段的放大器电路的方法包括在预充电阶段期间将第一和第二电容器充电到第一和第二偏置电压。第一电容器耦合到具有第二输入和输出的放大器电路的第一输入端。第二电容器耦合到第二输入端。在采样/转换阶段期间，放大器电路的第一输入通过第一电容耦合到输入信号，以根据第一偏置电压对输入信号进行电平移位，并且放大器的输出端通过所述第二电容器根据所述第二偏置电压对反馈信号进行电平移位。

33. 发明申请

US20130222162A1 DIGITAL TO ANALOG CONVERTER 有权
标题翻译：数字到模拟转换器
公开(公告)号：US20130222162A1
公开(公告)日：2013-08-29
申请号：US13408173
申请日：2012-02-29
申请人： Jinwen Xiao , Pavel Konecny , Axel Thomsen , Ka Y. Leung
发明人： Jinwen Xiao , Pavel Konecny , Axel Thomsen , Ka Y. Leung
IPC分类号： H03M1/10 , H03M1/66
CPC分类号： H03M1/1047 , H03M1/745 , H03M1/785
摘要： An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.
摘要翻译：使用主数模转换器（DAC）和子DAC将输入数字信号转换为模拟信号。从输入数字信号中减去偏移值，以生成偏移调整数字信号。主DAC将偏移调整后的数字信号转换为第一个模拟信号。基于偏移值和至少部分地在主DAC的校准期间确定的校正因子来生成第二数字信号。子DAC将第二数字转换为第二模拟信号，当与第一模拟信号组合时，其提供输入数字信号的模拟表示。

34. 发明授权

US08471629B2 Providing automatic power control for a power amplifier 有权
标题翻译：为功率放大器提供自动功率控制
公开(公告)号：US08471629B2
公开(公告)日：2013-06-25
申请号：US13173791
申请日：2011-06-30
申请人： Axel Thomsen , Zhongda Wang , Sai Chu Wong , Yunteng Huang
发明人： Axel Thomsen , Zhongda Wang , Sai Chu Wong , Yunteng Huang
IPC分类号： H03F1/14 , H03G3/20
CPC分类号： H03G3/34 , H03G3/3042
摘要： A power control circuit is coupled to receive a feedback signal from a power amplifier (PA) and generate a control signal to control a variable gain amplifier (VGA) coupled to an input to the PA based on the feedback signal. The power control circuit may include, in one embodiment, a mute circuit to generate a mute signal to be provided to the VGA when the control signal is less than a first level and a clamp circuit to clamp a control voltage used to generate the control signal from exceeding a threshold level.
摘要翻译：功率控制电路被耦合以从功率放大器（PA）接收反馈信号，并产生控制信号，以根据反馈信号控制耦合到PA的输入的可变增益放大器（VGA）。在一个实施例中，功率控制电路可以包括静音电路，以在控制信号小于第一电平时产生要提供给VGA的静音信号，以及钳位电路来钳位用于产生控制信号的控制电压超过阈值水平。

35. 发明申请

US20110050198A1 LOW-POWER VOLTAGE REGULATOR 审中-公开
标题翻译：低功率电压调节器
公开(公告)号：US20110050198A1
公开(公告)日：2011-03-03
申请号：US12551788
申请日：2009-09-01
申请人： Zhiwei Dong , William W. K. Tang , Axel Thomsen
发明人： Zhiwei Dong , William W. K. Tang , Axel Thomsen
IPC分类号： G05F3/16
CPC分类号： G05F3/242 , G05F1/607
摘要： A technique for reducing power dissipation and circuit area for a high voltage application includes creating a low-voltage, local power supply for use with local circuitry. In at least one embodiment of the invention, an apparatus includes an output node configured to provide a regulated output voltage. The apparatus includes a variable current source coupled to a first power supply node, wherein the variable current source is configured to provide an output current to the output node based on a control signal on a control node. The apparatus includes a feedback circuit configured to generate the control signal based on a mirrored current. The mirrored current is a mirrored version of a residual current flowing between the output node and a second power supply node. The regulated output voltage has a voltage level less than the voltage level on the first power supply node.
摘要翻译：用于降低功率耗散和高电压应用的电路面积的技术包括产生用于本地电路的低电压本地电源。在本发明的至少一个实施例中，一种装置包括被配置成提供调节输出电压的输出节点。该装置包括耦合到第一电源节点的可变电流源，其中可变电流源被配置为基于控制节点上的控制信号向输出节点提供输出电流。该装置包括被配置为基于镜像电流产生控制信号的反馈电路。镜像电流是在输出节点和第二电源节点之间流动的剩余电流的镜像版本。调节输出电压具有小于第一电源节点上的电压电平的电压电平。

36. 发明申请

US20100052826A1 ISOLATOR WITH COMPLEMENTARY CONFIGURABLE MEMORY 有权
标题翻译：隔离器配有相应的可配置存储器
公开(公告)号：US20100052826A1
公开(公告)日：2010-03-04
申请号：US12494618
申请日：2009-06-30
申请人： PHIL A. CALLAHAN , AHSAN JAVED , ZHIWEI DONG , AXEL THOMSEN , DONALD E. ALFANO , TIMOTHY DUPUIS , KA Y. LEUNG
发明人： PHIL A. CALLAHAN , AHSAN JAVED , ZHIWEI DONG , AXEL THOMSEN , DONALD E. ALFANO , TIMOTHY DUPUIS , KA Y. LEUNG
IPC分类号： H03H2/00
CPC分类号： H01L24/48 , H01L23/49503 , H01L23/4952 , H01L23/49575 , H01L23/642 , H01L23/66 , H01L24/06 , H01L24/49 , H01L25/0655 , H01L2223/6611 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48472 , H01L2224/49171 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H04B2203/5491 , H01L2224/45099 , H01L2924/00
摘要： An isolator that includes first and second substantially identical circuitry galvanically isolated from each other and each having at least one communications channel thereon for communicating signals across an isolation boundary therebetween and each of said first and second circuitry having configurable functionality associated with the operation thereof. A coupling device is provided for coupling signal across the isolation boundary between the at least one communication channels of the first and second circuitry. First and second configuration memories are provided, each associated with a respective one of the first and second circuitry. First and second configuration control devices are provided, each associated with a respective one of the first and second circuitry and each configuring the functionality of the associated one of the first and second circuitry. The first and second configurable memories have stored therein complementary configuration information to control each of the functionalities of the first and second circuitry to operate in a complementary manner for communication of signals across the isolation boundary.
摘要翻译：一种隔离器，其包括彼此电隔离的第一和第二基本相同的电路，并且每个具有至少一个用于在其间的隔离边界传送信号的通信信道，所述第一和第二电路中的每一个具有与其操作相关联的可配置功能。提供耦合装置用于在第一和第二电路的至少一个通信信道之间的隔离边界上耦合信号。提供第一和第二配置存储器，每个与第一和第二电路中的相应一个相关联。提供第一和第二配置控制设备，每个配置控制设备与第一和第二电路中的相应一个相关联，并且每个配置控制设备配置第一和第二电路中相关联的一个的功能。第一和第二可配置存储器在其中存储有互补配置信息，以控制第一和第二电路的每个功能以互补的方式进行操作，用于跨越隔离边界的信号通信。

37. 发明授权

US07639002B1 Non-invasive, low pin count test circuits and methods 有权
标题翻译：非侵入性，低引脚数测试电路和方法
公开(公告)号：US07639002B1
公开(公告)日：2009-12-29
申请号：US11410362
申请日：2006-04-25
申请人： Murari Kejariwal , Prisad Ammisetti , Axel Thomsen , John Laurence Melanson
发明人： Murari Kejariwal , Prisad Ammisetti , Axel Thomsen , John Laurence Melanson
IPC分类号： G01R31/28
CPC分类号： G01R31/31707
摘要： A method of testing an integrated circuit including a plurality of test nodes includes initiating a test mode and, during a first time interval of the test mode, stepping a level of a supply current of the integrated circuit to a calibration level. Parameters are observed at the plurality of test nodes to detect errors during a second time interval of the test mode and the level of the supply current selectively stepped in response to a number of errors detected. The level of the supply current is decoded to identify the detected errors.
摘要翻译：一种测试包括多个测试节点的集成电路的方法包括启动测试模式，并且在测试模式的第一时间间隔期间，使集成电路的电源电平的级别达到校准水平。在多个测试节点处观察参数以在测试模式的第二时间间隔期间检测错误，并且响应于检测到的错误的数量选择性地步进电源电平。电源电流的电平被解码以识别检测到的错误。

38. 发明申请

US20080211588A1 Phase Error Cancellation 有权
标题翻译：相位误差消除
公开(公告)号：US20080211588A1
公开(公告)日：2008-09-04
申请号：US11571077
申请日：2005-06-28
申请人： Douglas R. Frey , Axel Thomsen , Ligang Zhang
发明人： Douglas R. Frey , Axel Thomsen , Ligang Zhang
IPC分类号： H03L7/00 , H03B5/30
CPC分类号： H03L7/0891 , H03L7/1976
摘要： A noise cancellation signal is generated for a fractional-N phase-locked loop (200). A divide value is provided to a first delta sigma modulator circuit (203), which generates a divide control signal to control a divide value of a feedback divider (208) in the phase-locked loop. An error term (e) is generated that is indicative of a difference between the generated divide control signal and the divide value supplied to the first delta sigma modulator circuit. The error term is integrated in an integrator (320) to generate an integrated error term (x), where xk+1=xk+ek; and a phase error correction circuit (209) utilizes the error term ek and the integrated error term xk to generate the phase error cancellation signal.
摘要翻译：对于分数N锁相环（200）产生噪声消除信号。分频值被提供给第一ΔΣ调制器电路（203），其产生除法控制信号以控制锁相环中的反馈分频器（208）的除法值。生成指示所生成的除法控制信号和提供给第一ΔΣ调制器电路的除法值之间的差异的误差项（e）。误差项被集成在积分器（320）中，以产生积分误差项（x），其中x k + 1 + x + / SUP>; 并且相位误差校正电路（209）利用误差项e≠k和积分误差项x≠k来产生相位误差消除信号。

39. 发明授权

US07342460B2 Expanded pull range for a voltage controlled clock synthesizer 有权
标题翻译：电压控制时钟合成器的扩展拉范围
公开(公告)号：US07342460B2
公开(公告)日：2008-03-11
申请号：US11278326
申请日：2006-03-31
申请人： Jeffrey S. Batchelor , Axel Thomsen
发明人： Jeffrey S. Batchelor , Axel Thomsen
IPC分类号： H03L7/18
CPC分类号： H03L7/1976 , H03L1/026 , H03L1/027 , H03L7/0992 , H03L7/10 , H03L7/197 , H03L7/23
摘要： A technique provides a clock source that meets accuracy requirements, allows the use of a low cost resonator, provides a wide range of output frequencies, and provides suitable phase noise performance. The technique generates a clock signal having a target output frequency using a controllable oscillator having at least one continuous frequency range of operation. The technique dynamically adjusts a reference control value based on a voltage for adjusting a frequency of the clock signal around a frequency determined by the reference control value. The reference control value is adjusted to be approximately within the center of an actual pull range corresponding to the controllable oscillator and a voltage control input of the controllable oscillator. The effective pull range of the controllable oscillator is continuous across the at least one continuous frequency range of operation.
摘要翻译：一种技术提供了满足精度要求的时钟源，允许使用低成本谐振器，提供宽范围的输出频率，并提供合适的相位噪声性能。该技术使用具有至少一个连续的操作频率范围的可控振荡器来产生具有目标输出频率的时钟信号。该技术基于用于调整围绕由参考控制值确定的频率的时钟信号的频率的电压来动态地调整参考控制值。参考控制值被调整为大约在对应于可控振荡器的实际牵引范围的中心和可控振荡器的电压控制输入的中心。可控振荡器的有效牵引范围在至少一个连续的操作频率范围内是连续的。

40. 发明授权

US07288998B2 Voltage controlled clock synthesizer 有权
标题翻译：电压时钟合成器
公开(公告)号：US07288998B2
公开(公告)日：2007-10-30
申请号：US11270957
申请日：2005-11-10
申请人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Derrick C. Wei
发明人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Derrick C. Wei
IPC分类号： H03L7/00
CPC分类号： H03L7/0898 , H03L1/022 , H03L1/026 , H03L7/095 , H03L7/0992 , H03L7/197 , H03L7/1976 , H03L7/23 , H03L7/235 , H03L2207/50 , H04J3/0688
摘要： A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.
摘要翻译：电压控制时钟合成器包括接收定时参考信号的锁相环（PLL）电路，提供振荡器输出信号的可控振荡器电路，例如VCO，以及耦合到振荡器输出信号的反馈分频器电路。振荡器输出信号的频率部分地根据用于产生确定反馈分频器电路的分频比的第一数字控制信号的存储值来确定。存在于电压控制输入端的控制电压根据由存储的值确定的频率调整振荡器输出信号的频率。控制电压被转换为第二数字信号，并用于与所存储的值组合确定第一数字控制信号。

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